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Corrects delay for SN access.
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@ -191,12 +191,13 @@ class ConcreteMachine:
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// MARK: Z80::BusHandler
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forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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// The SN76489 will use its ready line to trigger the Z80's wait for three
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// cycles when accessed. M1 cycles are extended by a single cycle. Short-circuit
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// that whole piece of communications by just accruing the time here if applicable.
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// The SN76489 will use its ready line to trigger the Z80's wait, which will add
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// thirty-one (!) cycles when accessed. M1 cycles are extended by a single cycle.
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// This code works out the delay up front in order to simplify execution flow, though
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// technically this is a little duplicative.
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HalfCycles penalty(0);
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if(cycle.operation == CPU::Z80::PartialMachineCycle::Output && ((*cycle.address >> 5) & 7) == 7) {
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penalty = HalfCycles(6);
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if((cycle.operation == CPU::Z80::PartialMachineCycle::Output || cycle.operation == CPU::Z80::PartialMachineCycle::Input) && ((*cycle.address >> 5) & 7) == 7) {
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penalty = HalfCycles(62);
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} else if(cycle.operation == CPU::Z80::PartialMachineCycle::ReadOpcode) {
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penalty = HalfCycles(2);
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}
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