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Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.

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This commit is contained in:
Thomas Harte 2017-06-21 20:38:08 -04:00
parent 36e8a11505
commit 0e0ce379b4
6 changed files with 51 additions and 51 deletions
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16
Machines/ZX8081/ZX8081.cpp
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@ -27,7 +27,7 @@ Machine::Machine() :
clear_all_keys();
}
int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
int Machine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
int wait_cycles = 0;
int previous_counter = horizontal_counter_;
@ -61,7 +61,7 @@ int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
uint16_t address = cycle.address ? *cycle.address : 0;
bool is_opcode_read = false;
switch(cycle.operation) {
case CPU::Z80::MachineCycle::Operation::Output:
case CPU::Z80::PartialMachineCycle::Output:
set_vsync(false);
line_counter_ = 0;
@ -69,7 +69,7 @@ int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
if(!(address & 1)) nmi_is_enabled_ = is_zx81_;
break;
case CPU::Z80::MachineCycle::Operation::Input: {
case CPU::Z80::PartialMachineCycle::Input: {
uint8_t value = 0xff;
if(!(address&1)) {
set_vsync(true);
@ -85,14 +85,14 @@ int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
*cycle.value = value;
} break;
case CPU::Z80::MachineCycle::Operation::Interrupt:
case CPU::Z80::PartialMachineCycle::Interrupt:
line_counter_ = (line_counter_ + 1) & 7;
*cycle.value = 0xff;
horizontal_counter_ = 0;
break;
case CPU::Z80::MachineCycle::Operation::ReadOpcodeStart:
case CPU::Z80::MachineCycle::Operation::ReadOpcodeWait:
case CPU::Z80::PartialMachineCycle::ReadOpcodeStart:
case CPU::Z80::PartialMachineCycle::ReadOpcodeWait:
// The ZX80 and 81 signal an interrupt while refresh is active and bit 6 of the refresh
// address is low. The Z80 signals a refresh, providing the refresh address during the
// final two cycles of an opcode fetch. Therefore communicate a transient signalling
@ -114,7 +114,7 @@ int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
}
is_opcode_read = true;
case CPU::Z80::MachineCycle::Operation::Read:
case CPU::Z80::PartialMachineCycle::Read:
if(address < ram_base_) {
*cycle.value = rom_[address & rom_mask_];
} else {
@ -136,7 +136,7 @@ int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
}
break;
case CPU::Z80::MachineCycle::Operation::Write:
case CPU::Z80::PartialMachineCycle::Write:
if(address >= ram_base_) {
ram_[address & ram_mask_] = *cycle.value;
}

2
Machines/ZX8081/ZX8081.hpp
View File

@ -45,7 +45,7 @@ class Machine:
public:
Machine();
int perform_machine_cycle(const CPU::Z80::MachineCycle &cycle);
int perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle);
void flush();
void setup_output(float aspect_ratio);

18
OSBindings/Mac/Clock SignalTests/Bridges/TestMachineZ80.mm
View File

@ -11,7 +11,7 @@
#import "TestMachine+ForSubclassEyesOnly.h"
@interface CSTestMachineZ80 ()
- (void)testMachineDidPerformBusOperation:(CPU::Z80::MachineCycle::Operation)operation
- (void)testMachineDidPerformBusOperation:(CPU::Z80::PartialMachineCycle::Operation)operation
address:(uint16_t)address
value:(uint8_t)value
timeStamp:(int)time_stamp;
@ -23,7 +23,7 @@ class BusOperationHandler: public CPU::Z80::AllRAMProcessor::MemoryAccessDelegat
public:
BusOperationHandler(CSTestMachineZ80 *targetMachine) : target_(targetMachine) {}
void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &processor, CPU::Z80::MachineCycle::Operation operation, uint16_t address, uint8_t value, int time_stamp) {
void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &processor, CPU::Z80::PartialMachineCycle::Operation operation, uint16_t address, uint8_t value, int time_stamp) {
[target_ testMachineDidPerformBusOperation:operation address:address value:value timeStamp:time_stamp];
}
@ -178,34 +178,34 @@ static CPU::Z80::Register registerForRegister(CSTestMachineZ80Register reg) {
_processor->set_memory_access_delegate(captureBusActivity ? _busOperationHandler : nullptr);
}
- (void)testMachineDidPerformBusOperation:(CPU::Z80::MachineCycle::Operation)operation address:(uint16_t)address value:(uint8_t)value timeStamp:(int)timeStamp {
- (void)testMachineDidPerformBusOperation:(CPU::Z80::PartialMachineCycle::Operation)operation address:(uint16_t)address value:(uint8_t)value timeStamp:(int)timeStamp {
int length = timeStamp - _lastOpcodeTime;
_lastOpcodeTime = timeStamp;
if(self.captureBusActivity) {
CSTestMachineZ80BusOperationCapture *capture = [[CSTestMachineZ80BusOperationCapture alloc] init];
switch(operation) {
case CPU::Z80::MachineCycle::Operation::Write:
case CPU::Z80::PartialMachineCycle::Write:
capture.operation = CSTestMachineZ80BusOperationCaptureOperationWrite;
break;
case CPU::Z80::MachineCycle::Operation::Read:
case CPU::Z80::PartialMachineCycle::Read:
capture.operation = CSTestMachineZ80BusOperationCaptureOperationRead;
break;
case CPU::Z80::MachineCycle::Operation::Refresh:
case CPU::Z80::PartialMachineCycle::Refresh:
capture.operation = CSTestMachineZ80BusOperationCaptureOperationReadOpcode;
break;
case CPU::Z80::MachineCycle::Operation::Input:
case CPU::Z80::PartialMachineCycle::Input:
capture.operation = CSTestMachineZ80BusOperationCaptureOperationPortRead;
break;
case CPU::Z80::MachineCycle::Operation::Output:
case CPU::Z80::PartialMachineCycle::Output:
capture.operation = CSTestMachineZ80BusOperationCaptureOperationPortWrite;
break;
case CPU::Z80::MachineCycle::Operation::Internal:
case CPU::Z80::PartialMachineCycle::Internal:
capture.operation = CSTestMachineZ80BusOperationCaptureOperationInternalOperation;
break;

46
Processors/Z80/Z80.hpp
View File

@ -62,7 +62,7 @@ enum Flag: uint8_t {
Subclasses will be given the task of performing bus operations, allowing them to provide whatever interface they like
between a Z80 and the rest of the system. @c BusOperation lists the types of bus operation that may be requested.
*/
struct MachineCycle {
struct PartialMachineCycle {
enum Operation {
ReadOpcodeStart = 0,
ReadOpcodeWait,
@ -99,27 +99,27 @@ struct MachineCycle {
};
// Elemental bus operations
#define ReadOpcodeStart() {MachineCycle::ReadOpcodeStart, 2, &pc_.full, &operation_, false}
#define ReadOpcodeWait(length, f) {MachineCycle::ReadOpcodeWait, length, &pc_.full, &operation_, f}
#define Refresh(len) {MachineCycle::Refresh, len, &ir_.full, nullptr, false}
#define ReadOpcodeStart() {PartialMachineCycle::ReadOpcodeStart, 2, &pc_.full, &operation_, false}
#define ReadOpcodeWait(length, f) {PartialMachineCycle::ReadOpcodeWait, length, &pc_.full, &operation_, f}
#define Refresh(len) {PartialMachineCycle::Refresh, len, &ir_.full, nullptr, false}
#define ReadStart(addr, val) {MachineCycle::ReadStart, 2, &addr.full, &val, false}
#define ReadWait(l, addr, val, f) {MachineCycle::ReadWait, l, &addr.full, &val, f}
#define ReadEnd(addr, val) {MachineCycle::Read, 1, &addr.full, &val, false}
#define ReadStart(addr, val) {PartialMachineCycle::ReadStart, 2, &addr.full, &val, false}
#define ReadWait(l, addr, val, f) {PartialMachineCycle::ReadWait, l, &addr.full, &val, f}
#define ReadEnd(addr, val) {PartialMachineCycle::Read, 1, &addr.full, &val, false}
#define WriteStart(addr, val) {MachineCycle::WriteStart, 2, &addr.full, &val, false}
#define WriteWait(l, addr, val, f) {MachineCycle::WriteWait, l, &addr.full, &val, f}
#define WriteEnd(addr, val) {MachineCycle::Write, 1, &addr.full, &val, false}
#define WriteStart(addr, val) {PartialMachineCycle::WriteStart, 2, &addr.full, &val, false}
#define WriteWait(l, addr, val, f) {PartialMachineCycle::WriteWait, l, &addr.full, &val, f}
#define WriteEnd(addr, val) {PartialMachineCycle::Write, 1, &addr.full, &val, false}
#define InputStart(addr, val) {MachineCycle::InputStart, 2, &addr.full, &val, false}
#define InputWait(addr, val, f) {MachineCycle::InputWait, 1, &addr.full, &val, f}
#define InputEnd(addr, val) {MachineCycle::Input, 1, &addr.full, &val, false}
#define InputStart(addr, val) {PartialMachineCycle::InputStart, 2, &addr.full, &val, false}
#define InputWait(addr, val, f) {PartialMachineCycle::InputWait, 1, &addr.full, &val, f}
#define InputEnd(addr, val) {PartialMachineCycle::Input, 1, &addr.full, &val, false}
#define OutputStart(addr, val) {MachineCycle::OutputStart, 2, &addr.full, &val}
#define OutputWait(addr, val, f) {MachineCycle::OutputWait, 1, &addr.full, &val, f}
#define OutputEnd(addr, val) {MachineCycle::Output, 1, &addr.full, &val}
#define OutputStart(addr, val) {PartialMachineCycle::OutputStart, 2, &addr.full, &val}
#define OutputWait(addr, val, f) {PartialMachineCycle::OutputWait, 1, &addr.full, &val, f}
#define OutputEnd(addr, val) {PartialMachineCycle::Output, 1, &addr.full, &val}
#define IntAck(length, val) {MachineCycle::Interrupt, length, nullptr, &val}
#define IntAck(length, val) {PartialMachineCycle::Interrupt, length, nullptr, &val}
// A wrapper to express a bus operation as a micro-op
#define BusOp(op) {MicroOp::BusOperation, nullptr, nullptr, op}
@ -134,7 +134,7 @@ struct MachineCycle {
#define Input(addr, val) BusOp(InputStart(addr, val)), BusOp(InputWait(addr, val, false)), BusOp(InputWait(addr, val, true)), BusOp(InputEnd(addr, val))
#define Output(addr, val) BusOp(OutputStart(addr, val)), BusOp(OutputWait(addr, val, false)), BusOp(OutputWait(addr, val, true)), BusOp(OutputEnd(addr, val))
#define InternalOperation(len) {MicroOp::BusOperation, nullptr, nullptr, {MachineCycle::Internal, len}}
#define InternalOperation(len) {MicroOp::BusOperation, nullptr, nullptr, {PartialMachineCycle::Internal, len}}
/// A sequence is a series of micro-ops that ends in a move-to-next-program operation.
#define Sequence(...) { __VA_ARGS__, {MicroOp::MoveToNextProgram} }
@ -277,7 +277,7 @@ template <class T> class Processor {
Type type;
void *source;
void *destination;
MachineCycle machine_cycle;
PartialMachineCycle machine_cycle;
};
const MicroOp *scheduled_program_counter_;
@ -838,7 +838,7 @@ template <class T> class Processor {
/*!
Runs the Z80 for a supplied number of cycles.
@discussion Subclasses must implement @c perform_machine_cycle(const MachineCycle &cycle) .
@discussion Subclasses must implement @c perform_machine_cycle(const PartialMachineCycle &cycle) .
If it is a read operation then @c value will be seeded with the value 0xff.
@ -872,7 +872,7 @@ template <class T> class Processor {
while(1) {
while(bus_request_line_) {
static MachineCycle bus_acknowledge_cycle = {MachineCycle::Operation::BusAcknowledge, 1};
static PartialMachineCycle bus_acknowledge_cycle = {PartialMachineCycle::BusAcknowledge, 1};
number_of_cycles_ -= static_cast<T *>(this)->perform_machine_cycle(bus_acknowledge_cycle) + 1;
if(!number_of_cycles_) {
static_cast<T *>(this)->flush();
@ -1683,7 +1683,7 @@ template <class T> class Processor {
*/
void flush() {}
int perform_machine_cycle(const MachineCycle &cycle) {
int perform_machine_cycle(const PartialMachineCycle &cycle) {
return 0;
}
@ -1936,7 +1936,7 @@ template <class T> class Processor {
/*!
Returns the bus cycle that the Z80 is currently in the process of performing.
*/
// const MachineCycle &get_current_bus_cycle(int &cycles_since_start) {
// const PartialMachineCycle &get_current_bus_cycle(int &cycles_since_start) {
// }
};

18
Processors/Z80/Z80AllRAM.cpp
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@ -16,7 +16,7 @@ class ConcreteAllRAMProcessor: public AllRAMProcessor, public Processor<Concrete
public:
ConcreteAllRAMProcessor() : AllRAMProcessor() {}
inline int perform_machine_cycle(const MachineCycle &cycle) {
inline int perform_machine_cycle(const PartialMachineCycle &cycle) {
timestamp_ += cycle.length;
if(!cycle.is_terminal()) {
return 0;
@ -24,28 +24,28 @@ class ConcreteAllRAMProcessor: public AllRAMProcessor, public Processor<Concrete
uint16_t address = cycle.address ? *cycle.address : 0x0000;
switch(cycle.operation) {
case MachineCycle::Operation::ReadOpcodeStart:
case PartialMachineCycle::ReadOpcodeStart:
check_address_for_trap(address);
case MachineCycle::Operation::Read:
case PartialMachineCycle::Read:
*cycle.value = memory_[address];
break;
case MachineCycle::Operation::Write:
case PartialMachineCycle::Write:
memory_[address] = *cycle.value;
break;
case MachineCycle::Operation::Output:
case PartialMachineCycle::Output:
break;
case MachineCycle::Operation::Input:
case PartialMachineCycle::Input:
// This logic is selected specifically because it seems to match
// the FUSE unit tests. It might need factoring out.
*cycle.value = address >> 8;
break;
case MachineCycle::Operation::Internal:
case MachineCycle::Operation::Refresh:
case PartialMachineCycle::Internal:
case PartialMachineCycle::Refresh:
break;
case MachineCycle::Operation::Interrupt:
case PartialMachineCycle::Interrupt:
// A pick that means LD HL, (nn) if interpreted as an instruction but is otherwise
// arbitrary.
*cycle.value = 0x21;

2
Processors/Z80/Z80AllRAM.hpp
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@ -22,7 +22,7 @@ class AllRAMProcessor:
static AllRAMProcessor *Processor();
struct MemoryAccessDelegate {
virtual void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &processor, CPU::Z80::MachineCycle::Operation operation, uint16_t address, uint8_t value, int time_stamp) = 0;
virtual void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &processor, CPU::Z80::PartialMachineCycle::Operation operation, uint16_t address, uint8_t value, int time_stamp) = 0;
};
inline void set_memory_access_delegate(MemoryAccessDelegate *delegate) {
delegate_ = delegate;