mirror of
https://github.com/TomHarte/CLK.git
synced 2025-02-01 09:33:20 +00:00
Attempts to fix direct indirect indexed; not yet successful I think.
This commit is contained in:
parent
7dde7cc743
commit
0ed98cbfac
@ -171,6 +171,10 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
|
|||||||
data_buffer_ = instruction_buffer_;
|
data_buffer_ = instruction_buffer_;
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
|
case OperationCopyDataToInstruction:
|
||||||
|
instruction_buffer_ = data_buffer_;
|
||||||
|
continue;
|
||||||
|
|
||||||
case OperationCopyAToData:
|
case OperationCopyAToData:
|
||||||
if(m_flag()) {
|
if(m_flag()) {
|
||||||
data_buffer_.size = 1;
|
data_buffer_.size = 1;
|
||||||
|
@ -428,6 +428,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
|
|||||||
target(CycleFetchIncrementData); // AAL.
|
target(CycleFetchIncrementData); // AAL.
|
||||||
target(CycleFetchData); // AAH.
|
target(CycleFetchData); // AAH.
|
||||||
|
|
||||||
|
target(OperationCopyDataToInstruction);
|
||||||
target(OperationConstructAbsoluteYRead);
|
target(OperationConstructAbsoluteYRead);
|
||||||
target(CycleFetchIncorrectDataAddress); // IO.
|
target(CycleFetchIncorrectDataAddress); // IO.
|
||||||
|
|
||||||
|
@ -112,8 +112,9 @@ enum MicroOp: uint8_t {
|
|||||||
|
|
||||||
/// Copies the current program counter to the data buffer.
|
/// Copies the current program counter to the data buffer.
|
||||||
OperationCopyPCToData,
|
OperationCopyPCToData,
|
||||||
OperationCopyInstructionToData,
|
|
||||||
OperationCopyDataToPC,
|
OperationCopyDataToPC,
|
||||||
|
OperationCopyInstructionToData,
|
||||||
|
OperationCopyDataToInstruction,
|
||||||
|
|
||||||
/// Copies the current PBR to the data buffer.
|
/// Copies the current PBR to the data buffer.
|
||||||
OperationCopyPBRToData,
|
OperationCopyPBRToData,
|
||||||
|
Loading…
x
Reference in New Issue
Block a user