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https://github.com/TomHarte/CLK.git
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Post pixel clock.
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@ -16,15 +16,15 @@ using namespace Electron;
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VideoOutput::VideoOutput(const uint8_t *memory) :
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ram_(memory),
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crt_(128,
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crt_(h_total,
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1,
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Outputs::Display::Type::PAL50,
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Outputs::Display::InputDataType::Red1Green1Blue1) {
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crt_.set_visible_area(crt_.get_rect_for_area(
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312 - vsync_end,
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256,
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(h_total - hsync_end) >> 3,
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80,
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h_total - hsync_end,
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80 * 8,
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4.0f / 3.0f
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));
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}
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@ -56,8 +56,8 @@ uint8_t VideoOutput::run_for(const Cycles cycles) {
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// reverse-engineering of the Electron ULA. It should therefore be as accurate to the
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// original hardware as my comprehension of VHDL and adaptation into sequential code allows.
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// Horizontal and vertical counter updates.
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const bool is_v_end = v_count_ == v_total();
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// Horizontal and vertical counter updates; code below should act
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const bool is_v_end = this->is_v_end();
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h_count_ += 8;
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if(h_count_ == h_total) {
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h_count_ = 0;
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@ -161,7 +161,7 @@ uint8_t VideoOutput::run_for(const Cycles cycles) {
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initial_output_target_ = current_output_target_ = crt_.begin_data(static_cast<size_t>(screen_pitch_));
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}
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}
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++output_length_;
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output_length_ += 8;
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if(output_ == OutputStage::Pixels && (!mode_40_ || h_count_ & 8) && current_output_target_) {
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const uint8_t data = ram_[byte_addr_ | char_row_];
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@ -171,5 +171,10 @@ class VideoOutput {
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bool in_blank() const {
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return h_count_ >= h_active || (mode_text_ && v_count_ >= v_active_txt) || (!mode_text_ && v_count_ >= v_active_gph) || char_row_ >= 8;
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}};
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}
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bool is_v_end() const {
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return v_count_ == v_total();
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}
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};
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}
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