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Start mutating towards a form that owns the switch.
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Thomas Harte
parent
954d920b9e
commit
0fe2c1406b
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@ -11,10 +11,151 @@
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#include "Model.hpp"
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#include "Operation.hpp"
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#include "../../Reflection/Dispatcher.hpp"
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#include <array>
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namespace InstructionSet::ARM {
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enum class ShiftType {
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LogicalLeft = 0b00,
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LogicalRight = 0b01,
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ArithmeticRight = 0b10,
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RotateRight = 0b11,
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};
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static constexpr int FlagsStartBit = 20;
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template <int position>
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constexpr bool flag_bit(uint8_t flags) {
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static_assert(position >= 20 && position < 28);
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return flags & (1 << (position - FlagsStartBit));
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}
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//
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// Data processing (i.e. AND to MVN).
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//
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struct DataProcessingFlags {
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constexpr DataProcessingFlags(uint8_t flags) noexcept : flags_(flags) {}
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/// @returns @c true if operand 2 is defined by the @c rotate() and @c immediate() fields;
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/// @c false if it is defined by the @c shift_*() and @c operand2() fields.
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constexpr bool operand2_is_immediate() { return flag_bit<25>(flags_); }
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constexpr bool set_condition_codes() { return flag_bit<20>(flags_); }
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private:
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uint8_t flags_;
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};
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struct DataProcessing {
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constexpr DataProcessing(uint32_t opcode) noexcept : opcode_(opcode) {}
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/// The destination register index. i.e. Rd.
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int destination() const { return (opcode_ >> 12) & 0xf; }
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/// The operand 1 register index. i.e. Rn.
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int operand1() const { return (opcode_ >> 16) & 0xf; }
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//
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// Register values for operand 2.
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//
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/// The operand 2 register index if @c operand2_is_immediate() is @c false; meaningless otherwise.
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int operand2() const { return opcode_ & 0xf; }
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/// The type of shift to apply to operand 2 if @c operand2_is_immediate() is @c false; meaningless otherwise.
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ShiftType shift_type() const { return ShiftType((opcode_ >> 5) & 3); }
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/// @returns @c true if the amount to shift by should be taken from a register; @c false if it is an immediate value.
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bool shift_count_is_register() const { return opcode_ & (1 << 4); }
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/// The shift amount register index if @c shift_count_is_register() is @c true; meaningless otherwise.
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int shift_register() const { return (opcode_ >> 8) & 0xf; }
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/// The amount to shift by if @c shift_count_is_register() is @c false; meaningless otherwise.
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int shift_amount() const { return (opcode_ >> 7) & 0x1f; }
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//
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// Immediate values for operand 2.
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//
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/// An 8-bit value to rotate right @c rotate() places if @c operand2_is_immediate() is @c true; meaningless otherwise.
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int immediate() const { return opcode_ & 0xff; }
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/// The number of bits to rotate @c immediate() by to the right if @c operand2_is_immediate() is @c true; meaningless otherwise.
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int rotate() const { return (opcode_ >> 7) & 0x1e; }
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private:
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uint32_t opcode_;
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};
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//
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// MUL and MLA.
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//
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struct MultiplyFlags {
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constexpr MultiplyFlags(uint8_t flags) noexcept : flags_(flags) {}
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constexpr bool set_condition_codes() { return flag_bit<20>(flags_); }
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private:
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uint8_t flags_;
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};
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struct Multiply {
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constexpr Multiply(uint32_t opcode) noexcept : opcode_(opcode) {}
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/// The destination register index. i.e. 'Rd'.
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int destination() const { return (opcode_ >> 16) & 0xf; }
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/// The accumulator register index for multiply-add. i.e. 'Rn'.
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int accumulator() const { return (opcode_ >> 12) & 0xf; }
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/// The multiplicand register index. i.e. 'Rs'.
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int multiplicand() const { return (opcode_ >> 8) & 0xf; }
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/// The multiplier register index. i.e. 'Rm'.
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int multiplier() const { return opcode_ & 0xf; }
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private:
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uint32_t opcode_;
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};
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struct OperationMapper {
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template <int i, typename SchedulerT> void dispatch(uint32_t instruction, SchedulerT &scheduler) {
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constexpr auto partial = static_cast<uint32_t>(i << 20);
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// Data processing; cf. p.17.
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if constexpr (((partial >> 26) & 0b11) == 0b00) {
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constexpr auto operation = Operation(int(Operation::AND) + ((partial >> 21) & 0xf));
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constexpr auto flags = DataProcessingFlags(i);
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scheduler.template data_processing<operation, flags>(
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DataProcessing(instruction)
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);
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return;
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}
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// Multiply and multiply-accumulate (MUL, MLA); cf. p.23.
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if(((partial >> 22) & 0b111'111) == 0b000'000) {
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if(((instruction >> 4) & 0b1111) != 0b1001) {
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scheduler.unknown(instruction);
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} else {
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constexpr bool is_mla = partial & (1 << 21);
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constexpr auto flags = MultiplyFlags(i);
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scheduler.template multiply<is_mla ? Operation::MLA : Operation::MUL, flags>(
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Multiply(instruction)
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);
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}
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return;
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}
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}
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};
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template <typename SchedulerT> void dispatch(uint32_t instruction, SchedulerT &scheduler) {
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OperationMapper mapper;
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Reflection::dispatch(mapper, (instruction >> 20) & 0xff, instruction, scheduler);
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}
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/*
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template <Model model>
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using OperationTable = std::array<Operation, 256>;
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@ -113,4 +254,6 @@ constexpr Operation operation(uint32_t opcode) {
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return op;
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}
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*/
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}
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@ -14,7 +14,7 @@
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namespace InstructionSet::ARM {
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enum class ShiftType {
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/*enum class ShiftType {
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LogicalLeft = 0b00,
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LogicalRight = 0b01,
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ArithmeticRight = 0b10,
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@ -140,7 +140,7 @@ class Instruction {
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private:
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uint32_t opcode_;
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};
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};*/
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// TODO: do MUL and MLA really transpose Rd and Rn as per the data sheet?
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// ARM: Assembly Language Programming by Cockerell thinks not.
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@ -44,39 +44,7 @@ enum class Operation {
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/// Rd = NOT Op2.
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MVN,
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/// Rd = Op1 AND Op2.
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ANDS,
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/// Rd = Op1 EOR Op2.
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EORS,
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/// Rd = Op1 - Op2.
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SUBS,
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/// Rd = Op2 - Op1.
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RSBS,
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/// Rd = Op1 + Op2.
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ADDS,
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/// Rd = Op1 + Ord2 + C.
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ADCS,
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/// Rd = Op1 - Op2 + C.
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SBCS,
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/// Rd = Op2 - Op1 + C.
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RSCS,
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/// Set condition codes on Op1 AND Op2.
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TSTS,
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/// Set condition codes on Op1 EOR Op2.
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TEQS,
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/// Set condition codes on Op1 - Op2.
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CMPS,
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/// Set condition codes on Op1 + Op2.
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CMNS,
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/// Rd = Op1 OR Op2.
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ORRS,
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/// Rd = Op2
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MOVS,
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/// Rd = Op1 AND NOT Op2.
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BICS,
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/// Rd = NOT Op2.
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MVNS,
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MUL, MLA,
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B, BL,
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LDR, STR,
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@ -87,21 +55,8 @@ enum class Operation {
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CoprocessorDataTransfer,
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Undefined,
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// These are kept at the end for a minor decoding win; they can be only partially decoded
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// with the table-based decoder used elsewhere so a special case checks more bits upon
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// a MUL or MLA and keeping these at the end of the enum allows a single conditional to
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// determine whether the extra decoding is needed.
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//
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// See is_multiply below.
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MUL, MLA,
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MULS, MLAS,
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};
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constexpr bool is_multiply(Operation op) {
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return op >= Operation::MUL;
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}
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enum class Condition {
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EQ, NE, CS, CC,
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MI, PL, VS, VC,
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