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Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.

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This commit is contained in:
Thomas Harte 2017-06-20 22:25:00 -04:00
parent f85b46286e
commit 108da64562
2 changed files with 5 additions and 3 deletions
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4
OSBindings/Mac/Clock SignalTests/Z80MachineCycleTests.swift
View File

@ -164,8 +164,8 @@ class Z80MachineCycleTests: XCTestCase {
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .read, length: 3),
MachineCycle(operation: .internalOperation, length: 5),
MachineCycle(operation: .read, length: 3),
MachineCycle(operation: .read, length: 5),
MachineCycle(operation: .write, length: 3),
]
)
}

4
Processors/Z80/Z80.hpp
View File

@ -325,7 +325,9 @@ template <class T> class Processor {
#define LD_GROUP(r, ri) \
LD(r, bc_.bytes.high), LD(r, bc_.bytes.low), LD(r, de_.bytes.high), LD(r, de_.bytes.low), \
LD(r, index.bytes.high), LD(r, index.bytes.low), StdInstr(INDEX(), Read3(INDEX_ADDR(), ri)), LD(r, a_)
LD(r, index.bytes.high), LD(r, index.bytes.low), \
StdInstr(INDEX(), Read3(INDEX_ADDR(), temp8_), {MicroOp::Move8, &temp8_, &ri}), \
LD(r, a_)
#define READ_OP_GROUP(op) \
StdInstr({MicroOp::op, &bc_.bytes.high}), StdInstr({MicroOp::op, &bc_.bytes.low}), \