From 108da64562cca02e0c86fc6d04c8028f6f90193e Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Tue, 20 Jun 2017 22:25:00 -0400 Subject: [PATCH] Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss. --- OSBindings/Mac/Clock SignalTests/Z80MachineCycleTests.swift | 4 ++-- Processors/Z80/Z80.hpp | 4 +++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/OSBindings/Mac/Clock SignalTests/Z80MachineCycleTests.swift b/OSBindings/Mac/Clock SignalTests/Z80MachineCycleTests.swift index 1109db5d6..a8a115827 100644 --- a/OSBindings/Mac/Clock SignalTests/Z80MachineCycleTests.swift +++ b/OSBindings/Mac/Clock SignalTests/Z80MachineCycleTests.swift @@ -164,8 +164,8 @@ class Z80MachineCycleTests: XCTestCase { MachineCycle(operation: .readOpcode, length: 4), MachineCycle(operation: .readOpcode, length: 4), MachineCycle(operation: .read, length: 3), - MachineCycle(operation: .internalOperation, length: 5), - MachineCycle(operation: .read, length: 3), + MachineCycle(operation: .read, length: 5), + MachineCycle(operation: .write, length: 3), ] ) } diff --git a/Processors/Z80/Z80.hpp b/Processors/Z80/Z80.hpp index 143a65b4a..70bc9d51a 100644 --- a/Processors/Z80/Z80.hpp +++ b/Processors/Z80/Z80.hpp @@ -325,7 +325,9 @@ template class Processor { #define LD_GROUP(r, ri) \ LD(r, bc_.bytes.high), LD(r, bc_.bytes.low), LD(r, de_.bytes.high), LD(r, de_.bytes.low), \ - LD(r, index.bytes.high), LD(r, index.bytes.low), StdInstr(INDEX(), Read3(INDEX_ADDR(), ri)), LD(r, a_) + LD(r, index.bytes.high), LD(r, index.bytes.low), \ + StdInstr(INDEX(), Read3(INDEX_ADDR(), temp8_), {MicroOp::Move8, &temp8_, &ri}), \ + LD(r, a_) #define READ_OP_GROUP(op) \ StdInstr({MicroOp::op, &bc_.bytes.high}), StdInstr({MicroOp::op, &bc_.bytes.low}), \