diff --git a/Processors/65816/65816.hpp b/Processors/65816/65816.hpp
index acb76ccf3..25837e6db 100644
--- a/Processors/65816/65816.hpp
+++ b/Processors/65816/65816.hpp
@@ -12,6 +12,8 @@
 #include <cstdint>
 #include <vector>
 
+#include "../RegisterSizes.hpp"
+
 namespace CPU {
 namespace WDC65816 {
 
diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp
index 8a1eea9e5..022e576a8 100644
--- a/Processors/65816/Implementation/65816Storage.cpp
+++ b/Processors/65816/Implementation/65816Storage.cpp
@@ -28,7 +28,8 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
 
 			case LDA:	case LDX:	case LDY:
 
-			case JMP:	case JSR:
+			// The access type for these is arbitrary, though consistency is beneficial.
+			case JMP:	case JSR:	case JML:
 			return AccessType::Read;
 
 			case STA:	case STX:	case STY:	case STZ:
@@ -200,6 +201,31 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
 		target(CycleFetchData);								// New PCH.
 		target(OperationPerform);							// [JSR]
 	}
+
+	// 3a. Absolute Indirect (a), JML.
+	static void absolute_indirect_jml(AccessType, bool, const std::function<void(MicroOp)> &target) {
+		target(CycleFetchIncrementPC);			// New AAL.
+		target(CycleFetchPC);					// New AAH.
+
+		target(OperationConstructAbsolute);		// Calculate data address.
+		target(CycleFetchIncrementData);		// New PCL
+		target(CycleFetchIncrementData);		// New PCH
+		target(CycleFetchData);					// New PBR
+
+		target(OperationPerform);				// [JML]
+	};
+
+	// 3b. Absolute Indirect (a), JMP.
+	static void absolute_indirect_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
+		target(CycleFetchIncrementPC);			// New AAL.
+		target(CycleFetchPC);					// New AAH.
+
+		target(OperationConstructAbsolute);		// Calculate data address.
+		target(CycleFetchIncrementData);		// New PCL
+		target(CycleFetchData);					// New PCH
+
+		target(OperationPerform);				// [JMP]
+	};
 };
 
 ProcessorStorage TEMPORARY_test_instance;
@@ -324,7 +350,7 @@ ProcessorStorage::ProcessorStorage() {
 	/* 0x69 ADC # */
 	/* 0x6a ROR A */
 	/* 0x6b RTL s */
-	/* 0x6c JMP (a) */
+	/* 0x6c JMP (a) */			op(absolute_indirect_jmp, JMP);
 	/* 0x6d ADC a */			op(absolute, ADC);
 	/* 0x6e ROR a */
 	/* 0x6f ADC al */
@@ -443,7 +469,7 @@ ProcessorStorage::ProcessorStorage() {
 	/* 0xd9 CMP a, y */
 	/* 0xda PHX s */
 	/* 0xdb STP i */
-	/* 0xdc JMP (a) */
+	/* 0xdc JML (a) */			op(absolute_indirect_jml, JML);
 	/* 0xdd CMP a, x */
 	/* 0xde DEC a, x */
 	/* 0xdf CMP al, x */
diff --git a/Processors/65816/Implementation/65816Storage.hpp b/Processors/65816/Implementation/65816Storage.hpp
index d1f3dcf96..599689a6d 100644
--- a/Processors/65816/Implementation/65816Storage.hpp
+++ b/Processors/65816/Implementation/65816Storage.hpp
@@ -61,6 +61,9 @@ enum Operation: uint8_t {
 	/// Loads the PC with the operand from the data buffer.
 	JMP,
 
+	/// Loads the PC and PBR with the operand from the data buffer.
+	JML,
+
 	/// Loads the PC with the operand from the daa buffer, replacing
 	/// it with the old PC.
 	JSR,
@@ -86,6 +89,20 @@ class ProcessorStorage {
 	private:
 		friend ProcessorStorageConstructor;
 
+		// Registers.
+		RegisterPair16 a_;
+		RegisterPair16 x_, y_;
+		uint16_t pc_, s_;
+
+		// Not
+		uint16_t direct_;
+
+		// Banking registers are all stored with the relevant byte
+		// shifted up bits 16–23.
+		uint32_t data_bank_;	// i.e. DBR.
+		uint32_t program_bank_;	// i.e. PBR.
+
+
 		std::vector<MicroOp> micro_ops_;
 };