mirror of
https://github.com/TomHarte/CLK.git
synced 2025-02-27 00:30:26 +00:00
Quick fix: add one cycle to get to the genuine end of the line (i.e. after cycle 0, not on it). Not 3, with the video then becoming desynchronised from the CPU clock.
This commit is contained in:
parent
0124832876
commit
151c6b4421
@ -186,8 +186,8 @@ int Machine::perform_bus_operation(CPU6502::BusOperation operation, uint16_t add
|
||||
case 0x01: _vBlankEnabled = !!(*value & 0x02); break;
|
||||
|
||||
case 0x02: {
|
||||
cycle_count += (_horizontalTimer / 3)+3;
|
||||
output_pixels(_horizontalTimer+1);
|
||||
cycle_count += (_horizontalTimer / 3)+1;
|
||||
output_pixels(_horizontalTimer+3);
|
||||
} break;
|
||||
case 0x03: _horizontalTimer = 227; break;
|
||||
|
||||
|
Loading…
x
Reference in New Issue
Block a user