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mirror of https://github.com/TomHarte/CLK.git synced 2025-02-27 00:30:26 +00:00

Quick fix: add one cycle to get to the genuine end of the line (i.e. after cycle 0, not on it). Not 3, with the video then becoming desynchronised from the CPU clock.

This commit is contained in:
Thomas Harte 2015-07-30 00:00:35 -04:00
parent 0124832876
commit 151c6b4421

View File

@ -186,8 +186,8 @@ int Machine::perform_bus_operation(CPU6502::BusOperation operation, uint16_t add
case 0x01: _vBlankEnabled = !!(*value & 0x02); break;
case 0x02: {
cycle_count += (_horizontalTimer / 3)+3;
output_pixels(_horizontalTimer+1);
cycle_count += (_horizontalTimer / 3)+1;
output_pixels(_horizontalTimer+3);
} break;
case 0x03: _horizontalTimer = 227; break;