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Extended quality of known address read/write/modify mapping, and started recording internal accesses in addition to external.
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3101dc94a7
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@ -189,7 +189,7 @@ static void AddToDisassembly(PartialDisassembly &disassembly, const std::vector<
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break;
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case 0x87: case 0x97: case 0x83: case 0x8f:
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instruction.operation = Instruction::SAX;
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instruction.operation = Instruction::AXS;
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break;
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case 0xa7: case 0xb7: case 0xa3: case 0xb3: case 0xaf: case 0xbf:
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instruction.operation = Instruction::LAX;
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@ -205,7 +205,7 @@ static void AddToDisassembly(PartialDisassembly &disassembly, const std::vector<
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IM_INSTRUCTION(0x6b, Instruction::ARR)
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IM_INSTRUCTION(0x8b, Instruction::XAA)
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IM_INSTRUCTION(0xab, Instruction::LAX)
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IM_INSTRUCTION(0xcb, Instruction::AXS)
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IM_INSTRUCTION(0xcb, Instruction::SAX)
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IM_INSTRUCTION(0xeb, Instruction::SBC)
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case 0x93: case 0x9f:
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instruction.operation = Instruction::AHX;
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@ -259,16 +259,36 @@ static void AddToDisassembly(PartialDisassembly &disassembly, const std::vector<
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disassembly.disassembly.instructions_by_address[instruction.address] = instruction;
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// TODO: something wider-ranging than this
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if((instruction.addressing_mode == Instruction::Absolute || instruction.addressing_mode == Instruction::ZeroPage) && (instruction.operand < start_address || instruction.operand >= start_address + memory.size()))
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if(instruction.addressing_mode == Instruction::Absolute || instruction.addressing_mode == Instruction::ZeroPage)
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{
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if( instruction.operation == Instruction::STY ||
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instruction.operation == Instruction::STX ||
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instruction.operation == Instruction::STA)
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disassembly.disassembly.external_stores.insert(instruction.operand);
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if( instruction.operation == Instruction::LDY ||
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instruction.operation == Instruction::LDX ||
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instruction.operation == Instruction::LDA)
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disassembly.disassembly.external_loads.insert(instruction.operand);
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bool is_external = (instruction.operand&address_mask) < start_address || (instruction.operand&address_mask) >= start_address + memory.size();
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switch(instruction.operation)
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{
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default: break;
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case Instruction::LDY: case Instruction::LDX: case Instruction::LDA:
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case Instruction::LAX:
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case Instruction::AND: case Instruction::EOR: case Instruction::ORA: case Instruction::BIT:
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case Instruction::ADC: case Instruction::SBC:
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case Instruction::LAS:
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case Instruction::CMP: case Instruction::CPX: case Instruction::CPY:
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(is_external ? disassembly.disassembly.external_loads : disassembly.disassembly.internal_loads).insert(instruction.operand);
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break;
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case Instruction::STY: case Instruction::STX: case Instruction::STA:
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case Instruction::AXS: case Instruction::AHX: case Instruction::SHX: case Instruction::SHY:
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case Instruction::TAS:
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(is_external ? disassembly.disassembly.external_stores : disassembly.disassembly.internal_stores).insert(instruction.operand);
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break;
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case Instruction::SLO: case Instruction::RLA: case Instruction::SRE: case Instruction::RRA:
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case Instruction::DCP: case Instruction::ISC:
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case Instruction::INC: case Instruction::DEC:
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case Instruction::ASL: case Instruction::ROL: case Instruction::LSR: case Instruction::ROR:
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(is_external ? disassembly.disassembly.external_modifies : disassembly.disassembly.internal_modifies).insert(instruction.operand);
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break;
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}
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}
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// decide on overall flow control
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@ -65,6 +65,7 @@ struct Disassembly {
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std::map<uint16_t, Instruction> instructions_by_address;
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std::set<uint16_t> outward_calls;
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std::set<uint16_t> external_stores, external_loads, external_modifies;
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std::set<uint16_t> internal_stores, internal_loads, internal_modifies;
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};
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Disassembly Disassemble(const std::vector<uint8_t> &memory, uint16_t start_address, std::vector<uint16_t> entry_points, uint16_t address_mask = 0xffff);
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