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mirror of https://github.com/TomHarte/CLK.git synced 2024-07-29 00:29:28 +00:00

Added the most trivial implementation of the ZX81 wait line.

This commit is contained in:
Thomas Harte 2017-06-21 21:28:14 -04:00
parent 5e21c706f3
commit 15f6c51062

View File

@ -28,8 +28,6 @@ Machine::Machine() :
} }
int Machine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) { int Machine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
int wait_cycles = 0;
int previous_counter = horizontal_counter_; int previous_counter = horizontal_counter_;
horizontal_counter_ += cycle.length; horizontal_counter_ += cycle.length;
@ -39,26 +37,28 @@ int Machine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
if(nmi_is_enabled_) { if(nmi_is_enabled_) {
set_non_maskable_interrupt_line(true); set_non_maskable_interrupt_line(true);
if(!get_halt_line()) { if(!get_halt_line()) {
wait_cycles = vsync_end_cycle_ - horizontal_counter_; set_wait_line(true);
} }
} }
video_->run_for_cycles(horizontal_counter_ - vsync_start_cycle_ + wait_cycles); video_->run_for_cycles(horizontal_counter_ - vsync_start_cycle_);
} else if(previous_counter <= vsync_end_cycle_ && horizontal_counter_ > vsync_end_cycle_) { } else if(previous_counter <= vsync_end_cycle_ && horizontal_counter_ > vsync_end_cycle_) {
video_->run_for_cycles(vsync_end_cycle_ - previous_counter); video_->run_for_cycles(vsync_end_cycle_ - previous_counter);
set_hsync(false); set_hsync(false);
if(nmi_is_enabled_) set_non_maskable_interrupt_line(false); if(nmi_is_enabled_) {
set_non_maskable_interrupt_line(false);
set_wait_line(false);
}
video_->run_for_cycles(horizontal_counter_ - vsync_end_cycle_); video_->run_for_cycles(horizontal_counter_ - vsync_end_cycle_);
} else { } else {
video_->run_for_cycles(cycle.length); video_->run_for_cycles(cycle.length);
} }
horizontal_counter_ += wait_cycles;
if(is_zx81_) horizontal_counter_ %= 207; if(is_zx81_) horizontal_counter_ %= 207;
// tape_player_.run_for_cycles(cycle.length + wait_cycles); // tape_player_.run_for_cycles(cycle.length + wait_cycles);
if(!cycle.is_terminal()) { if(!cycle.is_terminal()) {
return wait_cycles; return 0;
} }
uint16_t address = cycle.address ? *cycle.address : 0; uint16_t address = cycle.address ? *cycle.address : 0;
@ -155,7 +155,7 @@ int Machine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
default: break; default: break;
} }
return wait_cycles; return 0;
} }
void Machine::flush() { void Machine::flush() {