6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-12-27 01:31:42 +00:00
Code Issues Projects Releases Wiki Activity

Fix PLD/PLB sizes.

Browse Source
This commit is contained in:
Thomas Harte 2024-09-21 21:28:38 -04:00
parent 9abd653fb9
commit 17ff0c4f65
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Processors/65816/Implementation/65816Storage.cpp
View File

@ -668,12 +668,12 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
}
// 22b(ii). Stack; s, PLx, ignoring emulation mode. I.e. PLD and PLB.
static void stack_pld_plb(AccessType, bool, const std::function<void(MicroOp)> &target) {
static void stack_pld_plb(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
target(CycleFetchPCThrowaway); // IO.
target(CycleFetchPCThrowaway); // IO.
target(CyclePullNotEmulation); // REG low.
target(CyclePullNotEmulation); // REG [high].
if(!is8bit) target(CyclePullNotEmulation); // REG low.
target(CyclePullNotEmulation); // REG [high].
target(OperationPerform);
}
@ -873,7 +873,7 @@ ProcessorStorage::ProcessorStorage() {
/* 0x28 PLP s */ op(stack_pull, PLP, AccessMode::Always8Bit);
/* 0x29 AND # */ op(immediate, AND);
/* 0x2a ROL A */ op(accumulator, ROL);
/* 0x2b PLD s */ op(stack_pld_plb, PLD);
/* 0x2b PLD s */ op(stack_pld_plb, PLD, AccessMode::Always16Bit);
/* 0x2c BIT a */ op(absolute, BIT);
/* 0x2d AND a */ op(absolute, AND);
/* 0x2e ROL a */ op(absolute_rmw, ROL);