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Finishes fleshing out [ADD/SUB]Q.
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@ -865,18 +865,18 @@ struct ProcessorStorageConstructor {
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switch(is_long_word_access ? l(mode) : bw(mode)) {
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default: continue;
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case bw(Dn):
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case bw(Dn): // [ADD/SUB]Q.bw #, Dn
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op(Action::PerformOperation, seq("np"));
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break;
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case l(Dn):
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case l(An):
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case bw(An):
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case l(Dn): // [ADD/SUB]Q.l #, Dn
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case l(An): // [ADD/SUB]Q.l #, An
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case bw(An): // [ADD/SUB]Q.bw #, An
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op(Action::PerformOperation, seq("np nn"));
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break;
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case bw(Ind):
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case bw(PostInc):
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case bw(Ind): // [ADD/SUB]Q.bw #, (An)
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case bw(PostInc): // [ADD/SUB]Q.bw #, (An)+
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op(Action::None, seq("nrd np", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("nw", { a(ea_register) }, !is_byte_access));
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if(mode == PostInc) {
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@ -884,14 +884,48 @@ struct ProcessorStorageConstructor {
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}
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break;
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case l(Ind):
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case l(PostInc):
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case l(PreDec): // [ADD/SUB]Q.l #, -(An)
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op(int(Action::Decrement4) | MicroOp::DestinationMask, seq("n"));
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case l(Ind): // [ADD/SUB]Q.l #, (An)
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case l(PostInc): // [ADD/SUB]Q.l #, (An)+
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op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("nRd+ nrd np", { ea(1), ea(1) }));
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op(Action::PerformOperation, seq("nw- nW", { ea(1), ea(1) }));
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if(mode == PostInc) {
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op(int(Action::Increment4) | MicroOp::DestinationMask);
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}
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break;
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case bw(PreDec): // [ADD/SUB]Q.bw #, -(An)
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op( int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::DestinationMask,
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seq("n nrd np", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("nw", { a(ea_register) }, !is_byte_access));
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break;
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case bw(d16An): // [ADD/SUB]Q.bw #, (d16, An)
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case bw(d8AnXn): // [ADD/SUB]Q.bw #, (d8, An, Xn)
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op(calc_action_for_mode(mode) | MicroOp::DestinationMask, seq(pseq("np nrd np", mode), { ea(1) }, !is_byte_access));
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op(Action::PerformOperation, seq("nw", { ea(1) }, !is_byte_access));
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break;
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case l(d16An): // [ADD/SUB]Q.l #, (d16, An)
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case l(d8AnXn): // [ADD/SUB]Q.l #, (d8, An, Xn)
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op(calc_action_for_mode(mode) | MicroOp::DestinationMask, seq(pseq("np nRd+ nrd np", mode), { ea(1), ea(1) }));
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op(Action::PerformOperation, seq("nw- nW", { ea(1), ea(1) }));
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break;
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case bw(XXXl): // [ADD/SUB]Q.bw #, (xxx).l
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op(Action::None, seq("np"));
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case bw(XXXw): // [ADD/SUB]Q.bw #, (xxx).w
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op(address_assemble_for_mode(mode) | MicroOp::DestinationMask, seq("np nrd np", { ea(1) }, !is_byte_access));
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op(Action::PerformOperation, seq("nw", { ea(1) }, !is_byte_access));
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break;
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case l(XXXl): // [ADD/SUB]Q.l #, (xxx).l
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op(Action::None, seq("np"));
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case l(XXXw): // [ADD/SUB]Q.l #, (xxx).w
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op(address_assemble_for_mode(mode) | MicroOp::DestinationMask, seq("np nRd+ nrd np", { ea(1), ea(1) }));
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op(Action::PerformOperation, seq("nw- nW", { ea(1), ea(1) }));
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break;
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}
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} break;
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