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Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.

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This commit is contained in:
Thomas Harte
2017-06-20 21:48:50 -04:00
parent b0375bb037
commit 184b371649
2 changed files with 15 additions and 1 deletions
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14
OSBindings/Mac/Clock SignalTests/Z80MachineCycleTests.swift
View File

@@ -156,6 +156,20 @@ class Z80MachineCycleTests: XCTestCase {
) )
} }
// LD (IX+d), n
func testLDIXdn() {
test(
program: [0xdd, 0x36, 0x10, 0x80],
busCycles: [
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .read, length: 3),
MachineCycle(operation: .internalOperation, length: 5),
MachineCycle(operation: .read, length: 3),
]
)
}
// LD A, (DE) // LD A, (DE)
func testLDADE() { func testLDADE() {
test( test(

2
Processors/Z80/Z80.hpp
View File

@@ -585,7 +585,7 @@ template <class T> class Processor {
/* 0x33 INC SP */ Instr(4, {MicroOp::Increment16, &sp_.full}), /* 0x33 INC SP */ Instr(4, {MicroOp::Increment16, &sp_.full}),
/* 0x34 INC (HL) */ StdInstr(INDEX(), Read4(INDEX_ADDR(), temp8_), {MicroOp::Increment8, &temp8_}, Write3(INDEX_ADDR(), temp8_)), /* 0x34 INC (HL) */ StdInstr(INDEX(), Read4(INDEX_ADDR(), temp8_), {MicroOp::Increment8, &temp8_}, Write3(INDEX_ADDR(), temp8_)),
/* 0x35 DEC (HL) */ StdInstr(INDEX(), Read4(INDEX_ADDR(), temp8_), {MicroOp::Decrement8, &temp8_}, Write3(INDEX_ADDR(), temp8_)), /* 0x35 DEC (HL) */ StdInstr(INDEX(), Read4(INDEX_ADDR(), temp8_), {MicroOp::Decrement8, &temp8_}, Write3(INDEX_ADDR(), temp8_)),
/* 0x36 LD (HL), n */ StdInstr({MicroOp::IndexedPlaceHolder}, ReadInc(pc_, temp8_), {MicroOp::CalculateIndexAddress, &index}, ReadInc(pc_, temp8_), Write3(INDEX_ADDR(), temp8_)), /* 0x36 LD (HL), n */ StdInstr(INDEX(), ReadInc(pc_, temp8_), Write3(INDEX_ADDR(), temp8_)),
/* 0x37 SCF */ StdInstr({MicroOp::SCF}), /* 0x37 SCF */ StdInstr({MicroOp::SCF}),
/* 0x38 JR C */ JR(TestC), /* 0x38 JR C */ JR(TestC),
/* 0x39 ADD HL, SP */ ADD16(index, sp_), /* 0x39 ADD HL, SP */ ADD16(index, sp_),