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mirror of https://github.com/TomHarte/CLK.git synced 2024-06-26 10:29:31 +00:00

Update use of logging.

This commit is contained in:
Thomas Harte 2024-01-19 22:14:24 -05:00
parent b61317ba7e
commit 18814f7b2c
4 changed files with 40 additions and 41 deletions

View File

@ -18,8 +18,6 @@
#include "../Utility/MemoryPacker.hpp"
#include "../Utility/MemoryFuzzer.hpp"
//#define NDEBUG
#define LOG_PREFIX "[Amiga] "
#include "../../Outputs/Log.hpp"
#include "Chipset.hpp"
@ -35,6 +33,8 @@ namespace {
constexpr int PALClockRate = 7'093'790;
//constexpr int NTSCClockRate = 7'159'090;
Log::Logger<Log::Source::Amiga> logger;
}
namespace Amiga {
@ -95,7 +95,7 @@ class ConcreteMachine:
// Check for assertion of reset.
if(cycle.operation & CPU::MC68000::Operation::Reset) {
memory_.reset();
LOG("Reset; PC is around " << PADHEX(8) << mc68000_.get_state().registers.program_counter);
logger.info().append("Reset; PC is around %08x", mc68000_.get_state().registers.program_counter);
}
// Autovector interrupts.
@ -142,7 +142,7 @@ class ConcreteMachine:
if(select_b) chipset_.cia_b.write(reg, cycle.value8_high());
}
// LOG("CIA " << (((address >> 12) & 3)^3) << " " << (operation & Microcycle::Read ? "read " : "write ") << std::dec << (reg & 0xf) << " of " << PADHEX(4) << +cycle.value16());
// logger.info().append("CIA %d %s %d of %04x", ((address >> 12) & 3)^3, operation & Microcycle::Read ? "read" : "write", reg & 0xf, cycle.value16());
} else if(address >= 0xdf'f000 && address <= 0xdf'f1be) {
chipset_.perform(cycle);
} else if(address >= 0xe8'0000 && address < 0xe9'0000) {
@ -158,9 +158,9 @@ class ConcreteMachine:
cycle.set_value16(0xffff);
}
// Don't log for the region that is definitely just ROM this machine doesn't have.
// Log only for the region that is definitely not just ROM this machine doesn't have.
if(address < 0xf0'0000) {
LOG("Unmapped " << (cycle.operation & CPU::MC68000::Operation::Read ? "read from " : "write to ") << PADHEX(6) << ((*cycle.address)&0xffffff) << " of " << cycle.value16());
logger.error().append("Unmapped %s %06x of %04x", cycle.operation & CPU::MC68000::Operation::Read ? "read from " : "write to ", (*cycle.address)&0xffffff, cycle.value16());
}
}
}

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@ -9,20 +9,16 @@
#include "Blitter.hpp"
#include "Minterms.hpp"
#include "../../Outputs/Log.hpp"
#include <cassert>
#ifndef NDEBUG
#define NDEBUG
#endif
#define LOG_PREFIX "[Blitter] "
#include "../../Outputs/Log.hpp"
using namespace Amiga;
namespace {
Log::Logger<Log::Source::AmigaBlitter> logger;
/// @returns Either the final carry flag or the output nibble when using fill mode given that it either @c is_exclusive fill mode, or isn't;
/// and the specified initial @c carry and input @c nibble.
template <bool wants_carry> constexpr uint32_t fill_nibble(bool is_exclusive, uint8_t carry, uint8_t nibble) {
@ -130,18 +126,18 @@ void Blitter<record_bus>::set_control(int index, uint16_t value) {
sequencer_.set_control(value >> 8);
}
shifts_[index] = value >> 12;
LOG("Set control " << index << " to " << PADHEX(4) << value);
logger.info().append("Set control %d to %04x", index, value);
}
template <bool record_bus>
void Blitter<record_bus>::set_first_word_mask(uint16_t value) {
LOG("Set first word mask: " << PADHEX(4) << value);
logger.info().append("Set first word mask: %04x", value);
a_mask_[0] = value;
}
template <bool record_bus>
void Blitter<record_bus>::set_last_word_mask(uint16_t value) {
LOG("Set last word mask: " << PADHEX(4) << value);
logger.info().append("Set last word mask: %04x", value);
a_mask_[1] = value;
}
@ -153,7 +149,7 @@ void Blitter<record_bus>::set_size(uint16_t value) {
if(!width_) width_ = 0x40;
height_ = value >> 6;
if(!height_) height_ = 1024;
LOG("Set size to " << std::dec << width_ << ", " << height_);
logger.info().append("Set size to %d, %d", width_, height_);
// Current assumption: writing this register informs the
// blitter that it should treat itself as about to start a new line.
@ -161,7 +157,7 @@ void Blitter<record_bus>::set_size(uint16_t value) {
template <bool record_bus>
void Blitter<record_bus>::set_minterms(uint16_t value) {
LOG("Set minterms " << PADHEX(4) << value);
logger.info().append("Set minterms: %02x", value & 0xff);
minterms_ = value & 0xff;
}
@ -178,7 +174,7 @@ void Blitter<record_bus>::set_minterms(uint16_t value) {
template <bool record_bus>
void Blitter<record_bus>::set_data(int channel, uint16_t value) {
LOG("Set data " << channel << " to " << PADHEX(4) << value);
logger.info().append("Set data %d to %04x", channel, value);
// Ugh, backed myself into a corner. TODO: clean.
switch(channel) {
@ -193,7 +189,7 @@ template <bool record_bus>
uint16_t Blitter<record_bus>::get_status() {
const uint16_t result =
(not_zero_flag_ ? 0x0000 : 0x2000) | (height_ ? 0x4000 : 0x0000);
LOG("Returned status of " << result);
logger.info().append("Returned status of %04x", result);
return result;
}

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@ -8,17 +8,16 @@
#include "Chipset.hpp"
#ifndef NDEBUG
#define NDEBUG
#endif
#define LOG_PREFIX "[Amiga chipset] "
#include "../../Outputs/Log.hpp"
#include <algorithm>
#include <cassert>
#include <tuple>
namespace {
Log::Logger<Log::Source::AmigaChipset> logger;
}
using namespace Amiga;
#define DMA_CONSTRUCT *this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1
@ -869,10 +868,10 @@ void Chipset::write(uint32_t address, uint16_t value, bool allow_conversion) {
break;
case 0x02a: // VPOSW
LOG("TODO: write vertical position high " << PADHEX(4) << value);
logger.error().append("TODO: write vertical position high %04x", value);
break;
case 0x02c: // VHPOSW
LOG("TODO: write vertical position low " << PADHEX(4) << value);
logger.error().append("TODO: write vertical position low %04x", value);
is_long_field_ = value & 0x8000;
break;
@ -887,11 +886,11 @@ void Chipset::write(uint32_t address, uint16_t value, bool allow_conversion) {
case 0x024: disk_.set_length(value); break; // DSKLEN
case 0x026: // DSKDAT
LOG("TODO: disk DMA; " << PADHEX(4) << value << " to " << address);
logger.error().append("TODO: disk DMA; %04x to %04x", value, address);
break;
case 0x09e: // ADKCON
LOG("Write disk control");
logger.info().append("Write disk control");
ApplySetClear(paula_disk_control_, 0x7fff);
disk_controller_.set_control(paula_disk_control_);
@ -905,7 +904,7 @@ void Chipset::write(uint32_t address, uint16_t value, bool allow_conversion) {
// Refresh.
case 0x028: // REFPTR
LOG("TODO (maybe): refresh; " << PADHEX(4) << value << " to " << PADHEX(8) << address);
logger.info().append("TODO (maybe): refresh; %04x to %08x", value, address);
break;
// Serial port.
@ -944,7 +943,7 @@ void Chipset::write(uint32_t address, uint16_t value, bool allow_conversion) {
break;
case 0x092: // DDFSTRT
if(fetch_window_[0] != value) {
LOG("Fetch window start set to " << std::dec << value);
logger.info().append("Fetch window start set to %d", value);
}
fetch_window_[0] = value & 0xfe;
break;
@ -952,7 +951,7 @@ void Chipset::write(uint32_t address, uint16_t value, bool allow_conversion) {
// TODO: something in my interpretation of ddfstart and ddfstop
// means a + 8 is needed below for high-res displays. Investigate.
if(fetch_window_[1] != value) {
LOG("Fetch window stop set to " << std::dec << fetch_window_[1]);
logger.info().append("Fetch window stop set to %d", fetch_window_[1]);
}
fetch_window_[1] = value & 0xfe;
break;
@ -989,7 +988,7 @@ void Chipset::write(uint32_t address, uint16_t value, bool allow_conversion) {
break;
case 0x106: // BPLCON3 (ECS)
LOG("TODO: Bitplane control; " << PADHEX(4) << value << " to " << PADHEX(8) << address);
logger.error().append("TODO: Bitplane control; %04x to %08x", value, address);
break;
case 0x108: bitplanes_.set_modulo<0>(value); break; // BPL1MOD
@ -1001,7 +1000,7 @@ void Chipset::write(uint32_t address, uint16_t value, bool allow_conversion) {
case 0x116:
case 0x118:
case 0x11a:
LOG("TODO: Bitplane data; " << PADHEX(4) << value << " to " << PADHEX(8) << address);
logger.error().append("TODO: Bitplane data; %04x to %08x", value, address);
break;
// Blitter.
@ -1056,7 +1055,7 @@ void Chipset::write(uint32_t address, uint16_t value, bool allow_conversion) {
case 0x088: copper_.reload<0>(); break;
case 0x08a: copper_.reload<1>(); break;
case 0x08c:
LOG("TODO: coprocessor instruction fetch identity " << PADHEX(4) << value);
logger.error().append("TODO: coprocessor instruction fetch identity %04x", value);
break;
// Sprites.
@ -1149,10 +1148,10 @@ uint16_t Chipset::read(uint32_t address, bool allow_conversion) {
// Disk DMA and control.
case 0x010: // ADKCONR
LOG("Read disk control");
logger.info().append("Read disk control");
return paula_disk_control_;
case 0x01a: // DSKBYTR
LOG("TODO: disk status");
logger.error().append("TODO: disk status");
assert(false); // Not yet implemented.
return 0xffff;
@ -1194,7 +1193,7 @@ Chipset::CIAAHandler::CIAAHandler(MemoryMap &map, DiskController &controller, Mo
void Chipset::CIAAHandler::set_port_output(MOS::MOS6526::Port port, uint8_t value) {
if(port) {
// CIA A, Port B: Parallel port output.
LOG("TODO: parallel output " << PADHEX(2) << +value);
logger.info().append("TODO: parallel output %02x", value);
} else {
// CIA A, Port A:
//
@ -1216,7 +1215,7 @@ void Chipset::CIAAHandler::set_port_output(MOS::MOS6526::Port port, uint8_t valu
uint8_t Chipset::CIAAHandler::get_port_input(MOS::MOS6526::Port port) {
if(port) {
LOG("TODO: parallel input?");
logger.info().append("TODO: parallel input?");
} else {
// Use the mouse as FIR0, the joystick as FIR1.
return
@ -1256,12 +1255,12 @@ void Chipset::CIABHandler::set_port_output(MOS::MOS6526::Port port, uint8_t valu
// b2: SEL
// b1: POUT
// b0: BUSY
LOG("TODO: DTR/RTS/etc: " << PADHEX(2) << +value);
logger.error().append("TODO: DTR/RTS/etc: %02x", value);
}
}
uint8_t Chipset::CIABHandler::get_port_input(MOS::MOS6526::Port) {
LOG("Unexpected: input for CIA B");
logger.error().append("Unexpected: input for CIA B");
return 0xff;
}

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@ -59,6 +59,8 @@ constexpr bool is_enabled(Source source) {
default: return true;
// The following are all things I'm not actively working on.
case Source::AmigaBlitter:
case Source::AmigaChipset:
case Source::AmigaCopper:
case Source::AmigaDisk:
case Source::IWM:
@ -74,6 +76,8 @@ constexpr const char *prefix(Source source) {
case Source::ADBDevice: return "ADB device";
case Source::ADBGLU: return "ADB GLU";
case Source::AmigaBlitter: return "Blitter";
case Source::AmigaChipset: return "Chipset";
case Source::AmigaCopper: return "Copper";
case Source::AmigaDisk: return "Disk";
case Source::AtariST: return "AtariST";