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Rephrased to allow non-conditional waits; expanded macros to cover all permitted lengths of read and write.
This commit is contained in:
Thomas Harte
parent
ebc7356db5
commit
194b7f60c5
@ -80,40 +80,58 @@ struct MachineCycle {
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int length;
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uint16_t *address;
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uint8_t *value;
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bool was_requested;
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};
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#define ReadOpcodeStart(addr, val) {MachineCycle::ReadOpcode, Phase::Start, 2, addr, val)
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#define ReadOpcodeWait(addr, val) {MachineCycle::ReadOpcode, Phase::Wait, 1, addr, val)
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#define Refresh(len) {MachineCycle::Refresh, Phase::Start, 2, &ir_.full, nullptr)
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// Elemental bus operations
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#define ReadOpcodeStart(addr, val) {MachineCycle::ReadOpcode, Phase::Start, 2, addr, val, false}
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#define ReadOpcodeWait(addr, val) {MachineCycle::ReadOpcode, Phase::Wait, 1, addr, val, true}
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#define Refresh(len) {MachineCycle::Refresh, Phase::Start, 2, &ir_.full, nullptr, false}
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#define ReadStart(addr, val) {MachineCycle::Read, Phase::Start, 2, addr, val)
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#define ReadWait(addr, val) {MachineCycle::Read, Phase::Wait, 1, addr, val)
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#define ReadEnd(addr, val) {MachineCycle::Read, Phase::End, 1, addr, val)
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#define ReadStart(addr, val) {MachineCycle::Read, Phase::Start, 2, addr, val, false}
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#define ReadWait(l, addr, val, f) {MachineCycle::Read, Phase::Wait, l, addr, val, f}
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#define ReadEnd(addr, val) {MachineCycle::Read, Phase::End, 1, addr, val, false}
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#define WriteStart(addr, val) {MachineCycle::Write, Phase::Start, 2, addr, val)
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#define WriteWait(addr, val) {MachineCycle::Write, Phase::Wait, 1, addr, val)
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#define WriteEnd(addr, val) {MachineCycle::Write, Phase::End, 1, addr, val)
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#define WriteStart(addr, val) {MachineCycle::Write, Phase::Start, 2, addr, val, false}
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#define WriteWait(l, addr, val, f) {MachineCycle::Write, Phase::Wait, l, addr, val, f}
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#define WriteEnd(addr, val) {MachineCycle::Write, Phase::End, 1, addr, val, false}
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#define InputStart(addr, val) {MachineCycle::Input, Phase::Start, 3, addr, val)
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#define InputWait(addr, val) {MachineCycle::Input, Phase::Wait, 1, addr, val)
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#define InputEnd(addr, val) {MachineCycle::Input, Phase::End, 1, addr, val)
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#define InputStart(addr, val) {MachineCycle::Input, Phase::Start, 2, addr, val, false}
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#define InputWait(addr, val, f) {MachineCycle::Input, Phase::Wait, 1, addr, val, f}
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#define InputEnd(addr, val) {MachineCycle::Input, Phase::End, 1, addr, val, false}
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#define OutpuStart(addr, val) {MachineCycle::Output, Phase::Start, 3, addr, val)
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#define OutpuWait(addr, val) {MachineCycle::Output, Phase::Wait, 1, addr, val)
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#define OutpuEnd(addr, val) {MachineCycle::Output, Phase::End, 1, addr, val)
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#define OutpuStart(addr, val) {MachineCycle::Output, Phase::Start, 2, addr, val}
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#define OutpuWait(addr, val, f) {MachineCycle::Output, Phase::Wait, 1, addr, val, f}
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#define OutpuEnd(addr, val) {MachineCycle::Output, Phase::End, 1, addr, val}
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// A wrapper to express a bus operation as a micro-op
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#define BusOp(c) {MicroOp::BusOperation, nullptr, nullptr, c}
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#define Read(addr, val) BusOp(ReadStart(addr, val)), BusOp(ReadWait(addr, val)), BusOp(ReadEnd(addr, val))
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#define Write(addr, val) BusOp(WriteStart(addr, val)), BusOp(WriteWait(addr, val)), BusOp(WriteEnd(addr, val))
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#define Input(addr, val) BusOp(InputStart(addr, val)), BusOp(InputWait(addr, val)), BusOp(InputEnd(addr, val))
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#define Output(addr, val) BusOp(OutputStart(addr, val)), BusOp(OutputWait(addr, val)), BusOp(OutputEnd(addr, val))
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// Compound bus operations, as micro-ops
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#define Read3(addr, val) BusOp(ReadStart(addr, val)), BusOp(ReadWait(1, addr, val, true)), BusOp(ReadEnd(addr, val))
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#define Read4(addr, val) BusOp(ReadStart(addr, val)), BusOp(ReadWait(1, addr, val, false)), BusOp(ReadWait(1, addr, val, true)), BusOp(ReadEnd(addr, val))
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#define Write3(addr, val) BusOp(WriteStart(addr, val)), BusOp(WriteWait(1, addr, val, true)), BusOp(WriteEnd(addr, val))
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#define Write5(addr, val) BusOp(WriteStart(addr, val)), BusOp(WriteWait(2, addr, val, false)), BusOp(WriteWait(1, addr, val, true)), BusOp(WriteEnd(addr, val))
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#define Input(addr, val) BusOp(InputStart(addr, val)), BusOp(InputWait(addr, val, false)), BusOp(InputWait(addr, val, true)), BusOp(InputEnd(addr, val))
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#define Output(addr, val) BusOp(OutputStart(addr, val)), BusOp(OutputWait(addr, val, false)), BusOp(OutputWait(addr, val, true)), BusOp(OutputEnd(addr, val))
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#define InternalOperation(n) BusOp({MachineCycle::Internal, n})
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/// A sequence is a series of micro-ops that ends in a move-to-next-program operation.
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#define Sequence(...) { __VA_ARGS__, {MicroOp::MoveToNextProgram} }
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/// An instruction is the part of an instruction that follows instruction fetch; it should include two or more refresh cycles and then the work of the instruction.
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#define Instr(r, ...) Sequence(BusOp(Refresh(r)), __VA_ARGS__)
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/// A standard instruction is one with the most normal timing: two cycles of refresh, then the work.
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#define StdInstr(...) Instr(2, __VA_ARGS_)
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// Assumption made: those instructions that are rated with an opcode fetch greater than four cycles spend the extra time
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// providing a lengthened refresh cycle. I assume this because the CPU doesn't have foresight and presumably spends the
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// normal refresh time decoding. So if it gets to cycle four and realises it has two more cycles of work, I have assumed
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// it simply maintains the refresh state for an extra two cycles.
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/*!
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@abstact An abstract base class for emulation of a Z80 processor via the curiously recurring template pattern/f-bounded polymorphism.
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@ -269,43 +287,30 @@ template <class T> class Processor {
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InstructionPage fdcb_page_;
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InstructionPage ddcb_page_;
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#define NOP {MicroOp::MoveToNextProgram}
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#define INDEX() {MicroOp::IndexedPlaceHolder}, FETCH(temp8_, pc_), WAIT(5), {MicroOp::CalculateIndexAddress, &index}
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#define FINDEX() {MicroOp::IndexedPlaceHolder}, FETCH(temp8_, pc_), {MicroOp::CalculateIndexAddress, &index}
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#define INDEX_ADDR() (add_offsets ? memptr_ : index)
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/* The following are helper macros that define common parts of instructions */
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#define Inc16(r) {(&r == &pc_) ? MicroOp::IncrementPC : MicroOp::Increment16, &r.full}
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#define INC16(r) {(&r == &pc_) ? MicroOp::IncrementPC : MicroOp::Increment16, &r.full}
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#define ReadInc(addr, val) Read(addr, val), INC16(y)
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#define WriteInc(addr, val) Write(addr, val), {MicroOp::Increment16, &y.full}
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/// Fetches into x from address y, and then increments y.
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#define FETCH(x, y) {MicroOp::BusOperation, nullptr, nullptr, {MachineCycle::Read, 3, &y.full, &x}}, INC16(y)
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/// Fetches into x from address y.
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#define FETCHL(x, y) {MicroOp::BusOperation, nullptr, nullptr, {MachineCycle::Read, 3, &y.full, &x}}
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#define Read16Inc(addr, val) ReadInc(addr, val.bytes.low), ReadInc(addr, val.bytes.high)
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#define Read16(addr, val) ReadInc(addr, val.bytes.low), Read(addr, val.bytes.high)
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/// Stores x to address y, and then increments y.
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#define STORE(x, y) {MicroOp::BusOperation, nullptr, nullptr, {MachineCycle::Write, 3, &y.full, &x}}, {MicroOp::Increment16, &y.full}
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/// Stores x to address y.
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#define STOREL(x, y) {MicroOp::BusOperation, nullptr, nullptr, {MachineCycle::Write, 3, &y.full, &x}}
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#define Write16(addr, val) WriteInc(addr, val.bytes.low), Write(addr, val.bytes.high)
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/// Fetches the 16-bit quantity x from address y, incrementing y twice.
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#define FETCH16(x, y) FETCH(x.bytes.low, y), FETCH(x.bytes.high, y)
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/// Fetches the 16-bit quantity x from address y, incrementing y once.
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#define FETCH16L(x, y) FETCH(x.bytes.low, y), FETCHL(x.bytes.high, y)
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#define INDEX() {MicroOp::IndexedPlaceHolder}, Read(pc_, temp8_), InternalOperation(5), {MicroOp::CalculateIndexAddress, &index}
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#define FINDEX() {MicroOp::IndexedPlaceHolder}, Read(pc_, temp8_), {MicroOp::CalculateIndexAddress, &index}
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#define INDEX_ADDR() (add_offsets ? memptr_ : index)
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/// Stores the 16-bit quantity x to address y, incrementing y once.
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#define STORE16L(x, y) STORE(x.bytes.low, y), STOREL(x.bytes.high, y)
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#define Push(x) {MicroOp::Decrement16, &sp_.full}, Write(sp_, x.bytes.high), {MicroOp::Decrement16, &sp_.full}, Write(sp_, x.bytes.low)
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#define Pop(x) Read(sp_, x.bytes.low), {MicroOp::Increment16, &sp_.full}, Read(sp_, x.bytes.high), {MicroOp::Increment16, &sp_.full}
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/// Outputs the 8-bit value to the 16-bit port
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#define OUT(port, value) {MicroOp::BusOperation, nullptr, nullptr, {MachineCycle::Output, 4, &port.full, &value}}
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/* The following are actual instructions */
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#define NOP Sequence(BusOp(Refresh(2)))
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/// Inputs the 8-bit value from the 16-bit port
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#define IN(port, value) {MicroOp::BusOperation, nullptr, nullptr, {MachineCycle::Input, 4, &port.full, &value}}
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#define PUSH(x) {MicroOp::Decrement16, &sp_.full}, STOREL(x.bytes.high, sp_), {MicroOp::Decrement16, &sp_.full}, STOREL(x.bytes.low, sp_)
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#define POP(x) FETCHL(x.bytes.low, sp_), {MicroOp::Increment16, &sp_.full}, FETCHL(x.bytes.high, sp_), {MicroOp::Increment16, &sp_.full}
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#define JP(cc) Program(FETCH16(temp16_, pc_), {MicroOp::cc}, {MicroOp::Move16, &temp16_.full, &pc_.full})
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#define CALL(cc) Program(FETCH16(temp16_, pc_), {MicroOp::cc}, WAIT(1), PUSH(pc_), {MicroOp::Move16, &temp16_.full, &pc_.full})
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#define JP(cc) StdInstr(Read16Inc(pc_, temp16_), {MicroOp::cc}, {MicroOp::Move16, &temp16_.full, &pc_.full})
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#define CALL(cc) StdInstr(Read16Inc(pc_, temp16_), {MicroOp::cc}, WAIT(1), PUSH(pc_), {MicroOp::Move16, &temp16_.full, &pc_.full})
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#define RET(cc) Program(WAIT(1), {MicroOp::cc}, POP(memptr_), {MicroOp::Move16, &memptr_.full, &pc_.full})
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#define JR(cc) Program(FETCH(temp8_, pc_), {MicroOp::cc}, WAIT(5), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full})
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#define RST() Program(WAIT(1), {MicroOp::CalculateRSTDestination}, PUSH(pc_), {MicroOp::Move16, &memptr_.full, &pc_.full})
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