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https://github.com/TomHarte/CLK.git
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In theory that's a full disassembler, at least as far as I want to go for now. Time to test.
This commit is contained in:
Thomas Harte
parent
a5fc45e66e
commit
1bffc70494
@ -23,7 +23,7 @@ static void AddToDisassembly(PartialDisassembly &disassembly, const std::vector<
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while(1)
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{
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uint16_t local_address = address - start_address;
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if(local_address > memory.size()) return;
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if(local_address >= memory.size()) return;
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address++;
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struct Instruction instruction;
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@ -82,6 +82,11 @@ static void AddToDisassembly(PartialDisassembly &disassembly, const std::vector<
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instruction.operation = op; \
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break;
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#define URM_INSTRUCTION(base, op) \
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case base+0x07: case base+0x17: case base+0x03: case base+0x13: case base+0x0f: case base+0x1f: case base+0x1b: \
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instruction.operation = op; \
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break;
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#define M_INSTRUCTION(base, op) \
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case base+0x0a: case base+0x06: case base+0x16: case base+0x0e: case base+0x1e: \
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instruction.operation = op; \
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@ -92,8 +97,21 @@ static void AddToDisassembly(PartialDisassembly &disassembly, const std::vector<
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switch(operation)
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{
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IM_INSTRUCTION(0x00, Instruction::BRK)
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IM_INSTRUCTION(0x20, Instruction::JSR)
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IM_INSTRUCTION(0x40, Instruction::RTI)
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IM_INSTRUCTION(0x60, Instruction::RTS)
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case 0x4c: case 0x6c:
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instruction.operation = Instruction::JMP;
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break;
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IM_INSTRUCTION(0x10, Instruction::BPL)
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IM_INSTRUCTION(0x30, Instruction::BMI)
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IM_INSTRUCTION(0x50, Instruction::BVC)
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IM_INSTRUCTION(0x70, Instruction::BVS)
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IM_INSTRUCTION(0x90, Instruction::BCC)
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IM_INSTRUCTION(0xb0, Instruction::BCS)
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IM_INSTRUCTION(0xd0, Instruction::BNE)
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IM_INSTRUCTION(0xf0, Instruction::BEQ)
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IM_INSTRUCTION(0xca, Instruction::DEX)
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IM_INSTRUCTION(0x88, Instruction::DEY)
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@ -120,9 +138,17 @@ static void AddToDisassembly(PartialDisassembly &disassembly, const std::vector<
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IM_INSTRUCTION(0x78, Instruction::SEI)
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IM_INSTRUCTION(0xb8, Instruction::CLV)
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URM_INSTRUCTION(0x00, Instruction::SLO)
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URM_INSTRUCTION(0x20, Instruction::RLA)
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URM_INSTRUCTION(0x40, Instruction::SRE)
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URM_INSTRUCTION(0x60, Instruction::RRA)
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RM_INSTRUCTION(0x00, Instruction::ORA)
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RM_INSTRUCTION(0x20, Instruction::AND)
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RM_INSTRUCTION(0x40, Instruction::EOR)
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case 0x24: case 0x2c:
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instruction.operation = Instruction::BIT;
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break;
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RM_INSTRUCTION(0x60, Instruction::ADC)
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RM_INSTRUCTION(0xc0, Instruction::CMP)
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RM_INSTRUCTION(0xe0, Instruction::SBC)
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@ -153,9 +179,104 @@ static void AddToDisassembly(PartialDisassembly &disassembly, const std::vector<
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case 0x84: case 0x94: case 0x8c:
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instruction.operation = Instruction::STY;
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break;
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case 0x04: case 0x0c: case 0x14: case 0x1a: case 0x1c:
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case 0x34: case 0x3a: case 0x3c: case 0x44: case 0x54: case 0x5a: case 0x5c:
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case 0x64: case 0x74: case 0x7a: case 0x7c:
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case 0x80: case 0x82: case 0x89:
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case 0xc2: case 0xd4: case 0xda: case 0xdc:
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case 0xe2: case 0xea: case 0xf4: case 0xfa: case 0xfc:
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instruction.operation = Instruction::NOP;
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break;
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case 0x87: case 0x97: case 0x83: case 0x8f:
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instruction.operation = Instruction::SAX;
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break;
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case 0xa7: case 0xb7: case 0xa3: case 0xb3: case 0xaf: case 0xbf:
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instruction.operation = Instruction::LAX;
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break;
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URM_INSTRUCTION(0xc0, Instruction::DCP)
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URM_INSTRUCTION(0xe0, Instruction::ISC)
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case 0x0b: case 0x2b:
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instruction.operation = Instruction::ANC;
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break;
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IM_INSTRUCTION(0x4b, Instruction::ALR)
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IM_INSTRUCTION(0x6b, Instruction::ARR)
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IM_INSTRUCTION(0x8b, Instruction::XAA)
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IM_INSTRUCTION(0xab, Instruction::LAX)
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IM_INSTRUCTION(0xcb, Instruction::AXS)
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IM_INSTRUCTION(0xeb, Instruction::SBC)
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case 0x93: case 0x9f:
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instruction.operation = Instruction::AHX;
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break;
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IM_INSTRUCTION(0x9c, Instruction::SHY)
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IM_INSTRUCTION(0x9e, Instruction::SHX)
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IM_INSTRUCTION(0x9b, Instruction::TAS)
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IM_INSTRUCTION(0xbb, Instruction::LAS)
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}
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#undef RM_INSTRUCTION
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#undef URM_INSTRUCTION
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#undef M_INSTRUCTION
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#undef IM_INSTRUCTION
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// get operand
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switch(instruction.addressing_mode)
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{
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// zero-byte operands
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case Instruction::Implied:
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instruction.operand = 0;
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break;
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// one-byte operands
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case Instruction::Immediate:
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case Instruction::ZeroPage: case Instruction::ZeroPageX: case Instruction::ZeroPageY:
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case Instruction::IndexedIndirectX: case Instruction::IndirectIndexedY:
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case Instruction::Relative:
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{
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uint16_t operand_address = address - start_address;
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if(operand_address >= memory.size()) return;
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address++;
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instruction.operand = memory[operand_address];
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}
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break;
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// two-byte operands
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case Instruction::Absolute: case Instruction::AbsoluteX: case Instruction::AbsoluteY:
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case Instruction::Indirect:
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{
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uint16_t operand_address = address - start_address;
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if(operand_address >= memory.size()-1) return;
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address += 2;
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instruction.operand = memory[operand_address] | (uint16_t)(memory[operand_address+1] << 8);
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}
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break;
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}
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// store the instruction away
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disassembly.disassembly.instructions_by_address[instruction.address] = instruction;
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// decide on overall flow control
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if(instruction.operation == Instruction::RTS || instruction.operation == Instruction::RTI) return;
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if(instruction.operation == Instruction::BRK) return; // TODO: check whether IRQ vector is within memory range
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if(instruction.operation == Instruction::JSR)
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{
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disassembly.remaining_entry_points.push_back(instruction.operand);
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}
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if(instruction.operation == Instruction::JMP)
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{
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if(instruction.addressing_mode == Instruction::Absolute)
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disassembly.remaining_entry_points.push_back(instruction.operand);
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return;
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}
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if(instruction.addressing_mode == Instruction::Relative)
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{
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uint16_t destination = (uint16_t)(address + (int8_t)instruction.operand);
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disassembly.remaining_entry_points.push_back(destination);
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}
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}
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}
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@ -21,13 +21,16 @@ namespace MOS6502 {
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struct Instruction {
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uint16_t address;
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enum {
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BRK, RTI, RTS,
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BRK, JSR, RTI, RTS, JMP,
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CLC, SEC, CLD, SED, CLI, SEI, CLV,
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NOP,
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KIL, SLO, ANC,
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AND, EOR, ORA,
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SLO, RLA, SRE, RRA, ALR, ARR,
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SAX, LAX, DCP, ISC,
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ANC, XAA, AXS,
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AND, EOR, ORA, BIT,
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ADC, SBC,
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AHX, SHY, SHX, TAS, LAS,
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LDA, STA, LDX, STX, LDY, STY,
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@ -37,14 +40,14 @@ struct Instruction {
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INC, DEC, DEX, DEY, INX, INY,
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ASL, ROL, LSR, ROR,
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TAX, TXA, TAY, TYA, TSX, TXS,
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PLA, PHA, PLP, PHP
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PLA, PHA, PLP, PHP,
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KIL
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} operation;
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enum {
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Absolute,
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AbsoluteX,
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AbsoluteY,
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AbsoluteIndirect,
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Accumulator,
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Immediate,
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Implied,
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ZeroPage,
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