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https://github.com/TomHarte/CLK.git
synced 2025-01-15 20:31:36 +00:00
Corrects and introduces new parts.
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d53d1c616f
commit
1d1e0d74f8
@ -139,13 +139,13 @@ void IWM::write(int address, uint8_t input) {
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case Q7|Q6|ENABLE: // Write data register.
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LOG("Data register write");
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// if(write_handshake_ & 0x80) {
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// shift_register_ = input;
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// output_bits_remaining_ = 8;
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// } else {
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// next_output_ = input;
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// write_handshake_ &= ~0x80;
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// }
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if(write_handshake_ & 0x80) {
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shift_register_ = input;
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output_bits_remaining_ = 8;
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} else {
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next_output_ = input;
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write_handshake_ &= ~0x80;
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}
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break;
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}
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}
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@ -282,7 +282,7 @@ void IWM::run_for(const Cycles cycles) {
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}
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break;
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/* case ShiftMode::Writing:
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case ShiftMode::Writing:
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while(cycles_since_shift_ + integer_cycles >= bit_length_) {
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const auto cycles_until_write = cycles_since_shift_ + integer_cycles - bit_length_;
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drives_[active_drive_]->run_for(cycles_until_write);
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@ -307,13 +307,14 @@ void IWM::run_for(const Cycles cycles) {
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}
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cycles_since_shift_ = integer_cycles;
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break;*/
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break;
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// case ShiftMode::CheckingWriteProtect:
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// while(--integer_cycles) {
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// shift_register_ = (shift_register_ >> 1) | sense();
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// }
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// break;
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case ShiftMode::CheckingWriteProtect:
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if(drive_is_rotating_[active_drive_]) drives_[active_drive_]->run_for(cycles);
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while(--integer_cycles) {
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shift_register_ = (shift_register_ >> 1) | sense();
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}
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break;
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default:
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if(drive_is_rotating_[active_drive_]) drives_[active_drive_]->run_for(cycles);
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@ -326,6 +327,8 @@ uint8_t IWM::sense() {
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}
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void IWM::process_event(const Storage::Disk::Drive::Event &event) {
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if(shift_mode_ != ShiftMode::Reading) return;
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switch(event.type) {
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case Storage::Disk::Track::Event::IndexHole: return;
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case Storage::Disk::Track::Event::FluxTransition:
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