From 1e4679ae1402c28a5a74c74a5fe822e006ea4e45 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Wed, 28 Oct 2020 17:25:40 -0400
Subject: [PATCH] Corrects `JSL` and `RTL`.

---
 Machines/Apple/AppleIIgs/AppleIIgs.cpp                  | 2 +-
 Processors/65816/Implementation/65816Implementation.hpp | 4 ++++
 Processors/65816/Implementation/65816Storage.cpp        | 6 +++---
 Processors/65816/Implementation/65816Storage.hpp        | 3 +++
 4 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/Machines/Apple/AppleIIgs/AppleIIgs.cpp b/Machines/Apple/AppleIIgs/AppleIIgs.cpp
index 6f2f734ec..080e3ee71 100644
--- a/Machines/Apple/AppleIIgs/AppleIIgs.cpp
+++ b/Machines/Apple/AppleIIgs/AppleIIgs.cpp
@@ -112,7 +112,7 @@ class ConcreteMachine:
 				}
 			}
 
-			printf("%06x [%02x]\n", address, *value);
+			printf("%06x [%02x] %c\n", address, *value, operation == CPU::WDC65816::BusOperation::ReadOpcode ? '*' : ' ');
 
 			Cycles duration = Cycles(5);
 
diff --git a/Processors/65816/Implementation/65816Implementation.hpp b/Processors/65816/Implementation/65816Implementation.hpp
index c8750a6e0..08902279b 100644
--- a/Processors/65816/Implementation/65816Implementation.hpp
+++ b/Processors/65816/Implementation/65816Implementation.hpp
@@ -626,6 +626,10 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
 							registers_.pc = uint16_t(data_buffer_.value);
 						break;
 
+						case RTL:
+							registers_.program_bank = data_buffer_.value & 0xff0000;
+						[[fallthrough]];
+
 						case RTS:
 							registers_.pc = uint16_t(data_buffer_.value + 1);
 						break;
diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp
index 06cff2dc7..0909cf79a 100644
--- a/Processors/65816/Implementation/65816Storage.cpp
+++ b/Processors/65816/Implementation/65816Storage.cpp
@@ -298,7 +298,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
 		target(CyclePush);						// PBR.
 		target(CycleAccessStack);				// IO.
 
-		target(CycleFetchIncrementPC);			// New PBR.
+		target(CycleFetchPC);					// New PBR.
 
 		target(OperationConstructAbsolute);		// Calculate data address.
 		target(OperationPerform);				// [JSL]
@@ -699,7 +699,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
 		target(CyclePull);				// New PCH.
 		target(CyclePull);				// New PBR.
 
-		target(OperationPerform);		// [JML, to perform the RTL]
+		target(OperationPerform);		// [RTL]
 	}
 
 	// 22j. Stack; s, BRK/COP.
@@ -867,7 +867,7 @@ ProcessorStorage::ProcessorStorage() {
 	/* 0x68 PLA s */			op(stack_pull, LDA);
 	/* 0x69 ADC # */			op(immediate, ADC);
 	/* 0x6a ROR A */			op(accumulator, ROR);
-	/* 0x6b RTL s */			op(stack_rtl, JML);
+	/* 0x6b RTL s */			op(stack_rtl, RTL);
 	/* 0x6c JMP (a) */			op(absolute_indirect_jmp, JMPind);
 	/* 0x6d ADC a */			op(absolute, ADC);
 	/* 0x6e ROR a */			op(absolute_rmw, ROR);
diff --git a/Processors/65816/Implementation/65816Storage.hpp b/Processors/65816/Implementation/65816Storage.hpp
index 3dc0c55a4..532433f87 100644
--- a/Processors/65816/Implementation/65816Storage.hpp
+++ b/Processors/65816/Implementation/65816Storage.hpp
@@ -220,6 +220,9 @@ enum Operation: uint8_t {
 
 	/// Loads the PC with the contents of the data buffer + 1.
 	RTS,
+
+	/// Loads the PC and program bank with the contents of the data buffer + 1.
+	RTL,
 };
 
 struct ProcessorStorageConstructor;