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mirror of https://github.com/TomHarte/CLK.git synced 2024-12-26 09:29:45 +00:00

Made an attempt properly to deal with initial bus state.

This commit is contained in:
Thomas Harte 2016-07-05 20:52:33 -04:00
parent 1bb109a23b
commit 1e6d90de17
2 changed files with 5 additions and 1 deletions

View File

@ -52,7 +52,7 @@ class SerialPortVIA: public MOS::MOS6522<SerialPortVIA>, public MOS::MOS6522IRQD
case ::Commodore::Serial::Line::Clock: _portB = (_portB & ~0x04) | (value ? 0 : 0x04); break;
case ::Commodore::Serial::Line::Attention:
_portB = (_portB & ~0x80) | (value ? 0 : 0x80);
set_control_line_input(Port::B, Line::Two, !!(value&0x80));
set_control_line_input(Port::B, Line::Two, value);
break;
}
}

View File

@ -13,10 +13,13 @@ using namespace Commodore::Serial;
void Bus::add_port(std::shared_ptr<Port> port)
{
_ports.push_back(port);
for(int line = (int)ServiceRequest; line <= (int)Reset; line++)
set_line_output_did_change((Line)line);
}
void Bus::set_line_output_did_change(Line line)
{
// i.e. I believe these lines to be open collector, active low
bool new_line_value = false;
for(std::weak_ptr<Port> port : _ports)
{
@ -27,6 +30,7 @@ void Bus::set_line_output_did_change(Line line)
}
}
// post an update only if one occurred
if(new_line_value != _line_values[line])
{
_line_values[line] = new_line_value;