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Corrects a couple of JSR and JMP addressing modes.
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@ -1535,18 +1535,18 @@ struct ProcessorStorageConstructor {
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case d16PC: // JSR (d16, PC)
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case d16An: // JSR (d16, An)
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op(Action::PrepareJSR);
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op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq("n np nW+ nw np", { ea(1), ea(1) }));
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op(Action::PerformOperation);
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op(calc_action_for_mode(mode) | MicroOp::SourceMask);
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op(Action::PerformOperation, seq("n np nW+ nw np", { ea(1), ea(1) }));
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break;
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case d8PCXn: // JSR (d8, PC, Xn)
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case d8AnXn: // JSR (d8, An, Xn)
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op(Action::PrepareJSR);
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op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq("n nn np nW+ nw np", { ea(1), ea(1) }));
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op(Action::PerformOperation);
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op(calc_action_for_mode(mode) | MicroOp::SourceMask);
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op(Action::PerformOperation, seq("n nn np nW+ nw np", { ea(1), ea(1) }));
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break;
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case XXXl: // JMP (xxx).L
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case XXXl: // JSR (xxx).L
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op(Action::None, seq("np"));
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op(Action::PrepareJSR);
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op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
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@ -1579,14 +1579,14 @@ struct ProcessorStorageConstructor {
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case d16PC: // JMP (d16, PC)
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case d16An: // JMP (d16, An)
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op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq("n np np"));
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op(Action::PerformOperation);
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op(calc_action_for_mode(mode) | MicroOp::SourceMask);
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op(Action::PerformOperation, seq("n np np"));
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break;
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case d8PCXn: // JMP (d8, PC, Xn)
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case d8AnXn: // JMP (d8, An, Xn)
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op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq("n nn np np"));
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op(Action::PerformOperation);
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op(calc_action_for_mode(mode) | MicroOp::SourceMask);
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op(Action::PerformOperation, seq("n nn np np"));
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break;
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case XXXl: // JMP (xxx).L
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