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https://github.com/TomHarte/CLK.git
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Merge pull request #576 from TomHarte/CRAMDots
Adds display of CRAM dots and enforces VRAM delays.
This commit is contained in:
Thomas Harte
GitHub
commit
1fc9356796
@ -73,11 +73,9 @@ Base::Base(Personality p) :
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mode_timing_.end_of_frame_interrupt_position.row = 193;
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}
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// Establish that output is 10 cycles after values have been read.
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// This is definitely correct for the TMS; more research may be
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// necessary for the other implemented VDPs.
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// Establish that output is delayed after reading by `output_lag` cycles.
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read_pointer_.row = 0;
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read_pointer_.column = 342 - 11; // i.e. 11 cycles behind the write pointer.
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read_pointer_.column = 342 - output_lag;
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write_pointer_.row = 1;
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write_pointer_.column = 0;
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}
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@ -93,7 +91,6 @@ TMS9918::TMS9918(Personality p):
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"}");
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crt_->set_video_signal(Outputs::CRT::VideoSignal::RGB);
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crt_->set_visible_area(Outputs::CRT::Rect(0.055f, 0.025f, 0.9f, 0.9f));
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crt_->set_input_gamma(2.8f);
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// The TMS remains in-phase with the NTSC colour clock; this is an empirical measurement
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// intended to produce the correct relationship between the hard edges between pixels and
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@ -187,6 +184,9 @@ void TMS9918::run_for(const HalfCycles cycles) {
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const int end_column = write_pointer_.column + write_cycles;
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LineBuffer &line_buffer = line_buffers_[write_pointer_.row];
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// Determine what this does to any enqueued VRAM access.
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minimum_access_column_ = write_pointer_.column + cycles_until_access_;
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cycles_until_access_ -= write_cycles;
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// ---------------------------------------
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@ -321,19 +321,34 @@ void TMS9918::run_for(const HalfCycles cycles) {
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if(read_cycles_pool) {
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// Determine how much time has passed in the remainder of this line, and proceed.
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const int read_cycles = std::min(342 - read_pointer_.column, read_cycles_pool);
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const int end_column = read_pointer_.column + read_cycles;
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LineBuffer &line_buffer = line_buffers_[read_pointer_.row];
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const int target_read_cycles = std::min(342 - read_pointer_.column, read_cycles_pool);
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int read_cycles_performed = 0;
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uint32_t next_cram_value = 0;
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while(read_cycles_performed < target_read_cycles) {
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const uint32_t cram_value = next_cram_value;
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next_cram_value = 0;
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int read_cycles = target_read_cycles - read_cycles_performed;
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if(!upcoming_cram_dots_.empty() && upcoming_cram_dots_.front().location.row == read_pointer_.row) {
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int time_until_dot = upcoming_cram_dots_.front().location.column - read_pointer_.column;
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if(time_until_dot < read_cycles) {
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read_cycles = time_until_dot;
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next_cram_value = upcoming_cram_dots_.front().value;
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upcoming_cram_dots_.erase(upcoming_cram_dots_.begin());
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}
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}
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if(!read_cycles) continue;
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read_cycles_performed += read_cycles;
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const int end_column = read_pointer_.column + read_cycles;
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LineBuffer &line_buffer = line_buffers_[read_pointer_.row];
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// TODO: actually perform these dots, at least in part by further subdividing
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// the period to run for.
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upcoming_cram_dots_.clear();
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// --------------------
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// Output video stream.
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// --------------------
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// --------------------
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// Output video stream.
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// --------------------
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#define intersect(left, right, code) \
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{ \
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@ -344,21 +359,37 @@ void TMS9918::run_for(const HalfCycles cycles) {
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}\
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}
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#define border(left, right) intersect(left, right, output_border(end - start))
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#define border(left, right) intersect(left, right, output_border(end - start, cram_value))
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if(line_buffer.line_mode == LineMode::Refresh || read_pointer_.row > mode_timing_.pixel_lines) {
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if(read_pointer_.row >= mode_timing_.first_vsync_line && read_pointer_.row < mode_timing_.first_vsync_line+4) {
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// Vertical sync.
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if(end_column == 342) {
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crt_->output_sync(342 * 4);
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if(line_buffer.line_mode == LineMode::Refresh || read_pointer_.row > mode_timing_.pixel_lines) {
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if(read_pointer_.row >= mode_timing_.first_vsync_line && read_pointer_.row < mode_timing_.first_vsync_line+4) {
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// Vertical sync.
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if(end_column == 342) {
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crt_->output_sync(342 * 4);
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}
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} else {
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// Right border.
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border(0, 15);
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// Blanking region; total length is 58 cycles,
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// and 58+15 = 73. So output the lot when the
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// cursor passes 73.
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if(read_pointer_.column < 73 && end_column >= 73) {
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crt_->output_blank(8*4);
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crt_->output_sync(26*4);
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crt_->output_blank(2*4);
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crt_->output_default_colour_burst(14*4);
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crt_->output_blank(8*4);
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}
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// Border colour for the rest of the line.
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border(73, 342);
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}
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} else {
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// Right border.
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border(0, 15);
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// Blanking region; total length is 58 cycles,
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// and 58+15 = 73. So output the lot when the
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// cursor passes 73.
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// Blanking region.
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if(read_pointer_.column < 73 && end_column >= 73) {
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crt_->output_blank(8*4);
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crt_->output_sync(26*4);
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@ -367,73 +398,58 @@ void TMS9918::run_for(const HalfCycles cycles) {
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crt_->output_blank(8*4);
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}
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// Border colour for the rest of the line.
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border(73, 342);
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}
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} else {
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// Right border.
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border(0, 15);
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// Left border.
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border(73, line_buffer.first_pixel_output_column);
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// Blanking region.
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if(read_pointer_.column < 73 && end_column >= 73) {
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crt_->output_blank(8*4);
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crt_->output_sync(26*4);
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crt_->output_blank(2*4);
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crt_->output_default_colour_burst(14*4);
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crt_->output_blank(8*4);
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}
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// Left border.
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border(73, line_buffer.first_pixel_output_column);
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// Pixel region.
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intersect(
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line_buffer.first_pixel_output_column,
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line_buffer.next_border_column,
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if(!asked_for_write_area_) {
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asked_for_write_area_ = true;
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pixel_origin_ = pixel_target_ = reinterpret_cast<uint32_t *>(
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crt_->allocate_write_area(static_cast<unsigned int>(line_buffer.next_border_column - line_buffer.first_pixel_output_column))
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);
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}
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if(pixel_target_) {
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const int relative_start = start - line_buffer.first_pixel_output_column;
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const int relative_end = end - line_buffer.first_pixel_output_column;
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switch(line_buffer.line_mode) {
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case LineMode::SMS: draw_sms(relative_start, relative_end, 0); break;
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case LineMode::Character: draw_tms_character(relative_start, relative_end); break;
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case LineMode::Text: draw_tms_text(relative_start, relative_end); break;
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case LineMode::Refresh: break; /* Dealt with elsewhere. */
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// Pixel region.
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intersect(
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line_buffer.first_pixel_output_column,
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line_buffer.next_border_column,
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if(!asked_for_write_area_) {
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asked_for_write_area_ = true;
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pixel_origin_ = pixel_target_ = reinterpret_cast<uint32_t *>(
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crt_->allocate_write_area(static_cast<unsigned int>(line_buffer.next_border_column - line_buffer.first_pixel_output_column))
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);
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}
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}
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if(end == line_buffer.next_border_column) {
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const unsigned int length = static_cast<unsigned int>(line_buffer.next_border_column - line_buffer.first_pixel_output_column);
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crt_->output_data(length * 4, length);
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pixel_origin_ = pixel_target_ = nullptr;
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asked_for_write_area_ = false;
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}
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);
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if(pixel_target_) {
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const int relative_start = start - line_buffer.first_pixel_output_column;
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const int relative_end = end - line_buffer.first_pixel_output_column;
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switch(line_buffer.line_mode) {
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case LineMode::SMS: draw_sms(relative_start, relative_end, cram_value); break;
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case LineMode::Character: draw_tms_character(relative_start, relative_end); break;
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case LineMode::Text: draw_tms_text(relative_start, relative_end); break;
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// Additional right border, if called for.
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if(line_buffer.next_border_column != 342) {
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border(line_buffer.next_border_column, 342);
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case LineMode::Refresh: break; /* Dealt with elsewhere. */
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}
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}
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if(end == line_buffer.next_border_column) {
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const unsigned int length = static_cast<unsigned int>(line_buffer.next_border_column - line_buffer.first_pixel_output_column);
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crt_->output_data(length * 4, length);
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pixel_origin_ = pixel_target_ = nullptr;
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asked_for_write_area_ = false;
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}
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);
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// Additional right border, if called for.
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if(line_buffer.next_border_column != 342) {
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border(line_buffer.next_border_column, 342);
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}
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}
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}
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#undef border
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#undef intersect
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// -------------
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// Advance time.
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// -------------
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read_pointer_.column = end_column;
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read_cycles_pool -= read_cycles;
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// -------------
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// Advance time.
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// -------------
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read_pointer_.column = end_column;
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}
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read_cycles_pool -= target_read_cycles;
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if(read_pointer_.column == 342) {
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read_pointer_.column = 0;
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read_pointer_.row = (read_pointer_.row + 1) % mode_timing_.total_lines;
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@ -444,16 +460,25 @@ void TMS9918::run_for(const HalfCycles cycles) {
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}
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}
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void Base::output_border(int cycles) {
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uint32_t *const pixel_target = reinterpret_cast<uint32_t *>(crt_->allocate_write_area(1));
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if(pixel_target) {
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if(is_sega_vdp(personality_)) {
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*pixel_target = master_system_.colour_ram[16 + background_colour_];
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} else {
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*pixel_target = palette[background_colour_];
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}
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void Base::output_border(int cycles, uint32_t cram_dot) {
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cycles *= 4;
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uint32_t border_colour =
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is_sega_vdp(personality_) ?
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master_system_.colour_ram[16 + background_colour_] :
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palette[background_colour_];
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if(cram_dot) {
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uint32_t *const pixel_target = reinterpret_cast<uint32_t *>(crt_->allocate_write_area(1));
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*pixel_target = border_colour | cram_dot;
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crt_->output_level(4);
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cycles -= 4;
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}
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if(cycles) {
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uint32_t *const pixel_target = reinterpret_cast<uint32_t *>(crt_->allocate_write_area(1));
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*pixel_target = border_colour;
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crt_->output_level(static_cast<unsigned int>(cycles));
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}
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crt_->output_level(static_cast<unsigned int>(cycles) * 4);
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}
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void TMS9918::set_register(int address, uint8_t value) {
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@ -465,6 +490,7 @@ void TMS9918::set_register(int address, uint8_t value) {
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// Enqueue the write to occur at the next available slot.
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read_ahead_buffer_ = value;
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queued_access_ = MemoryAccess::Write;
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cycles_until_access_ = vram_access_delay();
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return;
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}
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@ -487,11 +513,11 @@ void TMS9918::set_register(int address, uint8_t value) {
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write_phase_ = false;
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if(value & 0x80) {
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if(is_sega_vdp(personality_)) {
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if(value & 0x40) {
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master_system_.cram_is_selected = true;
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return;
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}
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value &= 0xf;
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if(value & 0x40) {
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master_system_.cram_is_selected = true;
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return;
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}
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value &= 0xf;
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} else {
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value &= 0x7;
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}
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@ -580,6 +606,7 @@ void TMS9918::set_register(int address, uint8_t value) {
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// A read request is enqueued upon setting the address; conversely a write
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// won't be enqueued unless and until some actual data is supplied.
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queued_access_ = MemoryAccess::Read;
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cycles_until_access_ = vram_access_delay();
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}
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master_system_.cram_is_selected = false;
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}
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@ -36,7 +36,7 @@ enum class TVStandard {
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NTSC
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};
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#define is_sega_vdp(x) x >= SMSVDP
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#define is_sega_vdp(x) ((x) >= SMSVDP)
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class Base {
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public:
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@ -51,6 +51,8 @@ class Base {
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}
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protected:
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const static int output_lag = 11; // i.e. pixel output will occur 11 cycles after corresponding data read.
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// The default TMS palette.
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const uint32_t palette[16] = {
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palette_pack(0, 0, 0),
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@ -89,6 +91,14 @@ class Base {
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enum class MemoryAccess {
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Read, Write, None
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} queued_access_ = MemoryAccess::None;
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int cycles_until_access_ = 0;
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int minimum_access_column_ = 0;
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int vram_access_delay() {
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// The Sega VDP seems to allow slightly quicker access;
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// Sega types generally claim 26 Z80 cycles are sufficient.
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// The received wisdom in MSX land is that it's 27.
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return is_sega_vdp(personality_) ? 7 : 8;
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}
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// Holds the main status register.
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uint8_t status_ = 0;
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@ -127,7 +137,7 @@ class Base {
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// A helper function to output the current border colour for
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// the number of cycles supplied.
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void output_border(int cycles);
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void output_border(int cycles, uint32_t cram_dot);
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// A struct to contain timing information for the current mode.
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struct {
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@ -326,7 +336,11 @@ class Base {
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}
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void do_external_slot(int access_column) {
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// TODO: is queued access ready yet?
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// Don't do anything if the required time for the access to become executable
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// has yet to pass.
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if(access_column < minimum_access_column_) {
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return;
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}
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switch(queued_access_) {
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default: return;
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@ -340,11 +354,24 @@ class Base {
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static_cast<uint8_t>(((read_ahead_buffer_ >> 4) & 3) * 255 / 3)
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);
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// Schedule a CRAM dot.
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// Schedule a CRAM dot; this is scheduled for wherever it should appear
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// on screen. So it's wherever the output stream would be now. Which
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// is output_lag cycles ago from the point of view of the input stream.
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upcoming_cram_dots_.emplace_back();
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CRAMDot &dot = upcoming_cram_dots_.back();
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dot.location.column = write_pointer_.column - output_lag;
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dot.location.row = write_pointer_.row;
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dot.location.column = access_column;
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// Handle before this row conditionally; then handle after (or, more realistically,
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// exactly at the end of) naturally.
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if(dot.location.column < 0) {
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--dot.location.row;
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dot.location.column += 342;
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}
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dot.location.row += dot.location.column / 342;
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dot.location.column %= 342;
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dot.value = master_system_.colour_ram[ram_pointer_ & 0x1f];
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} else {
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ram_[ram_pointer_ & 16383] = read_ahead_buffer_;
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