diff --git a/OSBindings/Mac/Clock SignalTests/68000Tests.mm b/OSBindings/Mac/Clock SignalTests/68000Tests.mm
index 1d880d26d..ec21d27ec 100644
--- a/OSBindings/Mac/Clock SignalTests/68000Tests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000Tests.mm	
@@ -1491,6 +1491,128 @@ class CPU::MC68000::ProcessorStorageTests {
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x3800);
 }
 
+// MARK: BCLR
+
+- (void)performBCLRD0D1:(uint32_t)d1 {
+	_machine->set_program({
+		0x0380		// BCLR D1, D0
+	});
+	auto state = _machine->get_processor_state();
+	state.data[0] = 0x12345678;
+	state.data[1] = d1;
+
+	_machine->set_processor_state(state);
+	_machine->run_for_instructions(1);
+
+	state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[1], d1);
+}
+
+- (void)testBCLR_D0D1_0 {
+	[self performBCLRD0D1:0];
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[0], 0x12345678);
+	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(_machine->get_cycle_count(), 8);
+}
+
+- (void)testBCLR_D0D1_10 {
+	[self performBCLRD0D1:10];
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[0], 0x12345278);
+	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(_machine->get_cycle_count(), 8);
+}
+
+- (void)testBCLR_D0D1_50 {
+	[self performBCLRD0D1:50];
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[0], 0x12305678);
+	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(_machine->get_cycle_count(), 10);
+}
+
+- (void)performBCLRD1Ind:(uint32_t)d1 {
+	_machine->set_program({
+		0x0390		// BCLR D1, (A0)
+	});
+	auto state = _machine->get_processor_state();
+	state.address[0] = 0x3000;
+	state.data[1] = d1;
+	*_machine->ram_at(0x3000) = 0x7800;
+
+	_machine->set_processor_state(state);
+	_machine->run_for_instructions(1);
+
+	state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[1], d1);
+	XCTAssertEqual(state.address[0], 0x3000);
+	XCTAssertEqual(_machine->get_cycle_count(), 12);
+}
+
+- (void)testBCLR_D1Ind_50 {
+	[self performBCLRD1Ind:50];
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7800);
+}
+
+- (void)testBCLR_D1Ind_3 {
+	[self performBCLRD1Ind:3];
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7000);
+}
+
+- (void)performBCLRImm:(uint16_t)immediate {
+	_machine->set_program({
+		0x0880, immediate		// BCLR #, D0
+	});
+	auto state = _machine->get_processor_state();
+	state.data[0] = 0x12345678;
+
+	_machine->set_processor_state(state);
+	_machine->run_for_instructions(1);
+
+	state = _machine->get_processor_state();
+	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+}
+
+- (void)testBCLR_Imm_28 {
+	[self performBCLRImm:28];
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[0], 0x02345678);
+	XCTAssertEqual(_machine->get_cycle_count(), 14);
+}
+
+- (void)testBCLR_Imm_4 {
+	[self performBCLRImm:4];
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[0], 0x12345668);
+	XCTAssertEqual(_machine->get_cycle_count(), 12);
+}
+
+- (void)testBCLR_ImmWWWx {
+	_machine->set_program({
+		0x08b8, 0x0006, 0x3000		// BCLR #6, ($3000).W
+	});
+	*_machine->ram_at(0x3000) = 0x7800;
+
+	_machine->run_for_instructions(1);
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(_machine->get_cycle_count(), 20);
+	XCTAssertEqual(*_machine->ram_at(0x3000), 0x3800);
+}
+
 // MARK: BSET
 
 - (void)performBSETD0D1:(uint32_t)d1 {
@@ -1612,6 +1734,122 @@ class CPU::MC68000::ProcessorStorageTests {
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7800);
 }
 
+// MARK: BTST
+
+- (void)performBTSTD0D1:(uint32_t)d1 {
+	_machine->set_program({
+		0x0300		// BTST D1, D0
+	});
+	auto state = _machine->get_processor_state();
+	state.data[0] = 0x12345678;
+	state.data[1] = d1;
+
+	_machine->set_processor_state(state);
+	_machine->run_for_instructions(1);
+
+	state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[0], 0x12345678);
+	XCTAssertEqual(state.data[1], d1);
+	XCTAssertEqual(6, _machine->get_cycle_count());
+}
+
+- (void)testBTST_D0D1_0 {
+	[self performBTSTD0D1:0];
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+}
+
+- (void)testBTST_D0D1_10 {
+	[self performBTSTD0D1:10];
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+}
+
+- (void)testBTST_D0D1_49 {
+	[self performBTSTD0D1:49];
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+}
+
+- (void)performBTSTD1Ind:(uint32_t)d1 {
+	_machine->set_program({
+		0x0310		// BTST D1, (A0)
+	});
+	auto state = _machine->get_processor_state();
+	state.address[0] = 0x3000;
+	state.data[1] = d1;
+	*_machine->ram_at(0x3000) = 0x7800;
+
+	_machine->set_processor_state(state);
+	_machine->run_for_instructions(1);
+
+	state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[1], d1);
+	XCTAssertEqual(state.address[0], 0x3000);
+	XCTAssertEqual(8, _machine->get_cycle_count());
+	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7800);
+}
+
+- (void)testBTST_D1Ind_50 {
+	[self performBTSTD1Ind:50];
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+}
+
+- (void)testBTST_D1Ind_3 {
+	[self performBTSTD1Ind:3];
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+}
+
+- (void)performBTSTImm:(uint16_t)immediate {
+	_machine->set_program({
+		0x0800, immediate		// BTST #, D0
+	});
+	auto state = _machine->get_processor_state();
+	state.data[0] = 0x12345678;
+
+	_machine->set_processor_state(state);
+	_machine->run_for_instructions(1);
+
+	state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[0], 0x12345678);
+	XCTAssertEqual(10, _machine->get_cycle_count());
+}
+
+- (void)testBTST_Imm_28 {
+	[self performBTSTImm:28];
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+}
+
+- (void)testBTST_Imm_2 {
+	[self performBTSTImm:2];
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+}
+
+- (void)testBTST_ImmWWWx {
+	_machine->set_program({
+		0x0838, 0x0006, 0x3000		// BTST #6, ($3000).W
+	});
+	*_machine->ram_at(0x3000) = 0x7800;
+
+	_machine->run_for_instructions(1);
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(_machine->get_cycle_count(), 16);
+	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7800);
+}
+
 // MARK: CHK
 
 - (void)performCHKd1:(uint32_t)d1 d2:(uint32_t)d2 {