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Added tests for the various LD (nn), rr instructions and corrected implementation to pass.

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This commit is contained in:
Thomas Harte 2017-07-22 11:39:13 -04:00
parent eaf313b0f6
commit 20a6bcc676
2 changed files with 62 additions and 5 deletions
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57
OSBindings/Mac/Clock SignalTests/Z80MemptrTests.swift
View File

@ -60,4 +60,61 @@ class Z80MemptrTests: XCTestCase {
}
}
// LD (addr), rp
func testLDnnrp() {
var hlBaseProgram: [UInt8] = [
0x22, 0x00, 0x00
]
var bcEDProgram: [UInt8] = [
0xed, 0x43, 0x00, 0x00
]
var deEDProgram: [UInt8] = [
0xed, 0x53, 0x00, 0x00
]
var hlEDProgram: [UInt8] = [
0xed, 0x63, 0x00, 0x00
]
var spEDProgram: [UInt8] = [
0xed, 0x73, 0x00, 0x00
]
var ixProgram: [UInt8] = [
0xdd, 0x22, 0x00, 0x00
]
var iyProgram: [UInt8] = [
0xfd, 0x22, 0x00, 0x00
]
for addr in 0 ..< 65536 {
hlBaseProgram[1] = UInt8(addr & 0x00ff)
hlBaseProgram[2] = UInt8(addr >> 8)
bcEDProgram[2] = UInt8(addr & 0x00ff)
bcEDProgram[3] = UInt8(addr >> 8)
deEDProgram[2] = UInt8(addr & 0x00ff)
deEDProgram[3] = UInt8(addr >> 8)
hlEDProgram[2] = UInt8(addr & 0x00ff)
hlEDProgram[3] = UInt8(addr >> 8)
spEDProgram[2] = UInt8(addr & 0x00ff)
spEDProgram[3] = UInt8(addr >> 8)
ixProgram[2] = UInt8(addr & 0x00ff)
ixProgram[3] = UInt8(addr >> 8)
iyProgram[2] = UInt8(addr & 0x00ff)
iyProgram[3] = UInt8(addr >> 8)
let expectedResult = UInt16((addr + 1) & 0xffff)
XCTAssertEqual(test(program: hlBaseProgram, length: 16, initialValue: 0xffff), expectedResult)
XCTAssertEqual(test(program: bcEDProgram, length: 20, initialValue: 0xffff), expectedResult)
XCTAssertEqual(test(program: deEDProgram, length: 20, initialValue: 0xffff), expectedResult)
XCTAssertEqual(test(program: hlEDProgram, length: 20, initialValue: 0xffff), expectedResult)
XCTAssertEqual(test(program: spEDProgram, length: 20, initialValue: 0xffff), expectedResult)
XCTAssertEqual(test(program: ixProgram, length: 20, initialValue: 0xffff), expectedResult)
XCTAssertEqual(test(program: iyProgram, length: 20, initialValue: 0xffff), expectedResult)
}
}
}

10
Processors/Z80/Z80.hpp
View File

@ -464,7 +464,7 @@ template <class T> class Processor {
NOP_ROW(), /* 0x20 */
NOP_ROW(), /* 0x30 */
/* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(bc_.bytes.high),
/* 0x42 SBC HL, BC */ SBC16(hl_, bc_), /* 0x43 LD (nn), BC */ StdInstr(Read16Inc(pc_, temp16_), Write16(temp16_, bc_)),
/* 0x42 SBC HL, BC */ SBC16(hl_, bc_), /* 0x43 LD (nn), BC */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, bc_)),
/* 0x44 NEG */ StdInstr({MicroOp::NEG}), /* 0x45 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
/* 0x46 IM 0 */ StdInstr({MicroOp::IM}), /* 0x47 LD I, A */ Instr(3, {MicroOp::Move8, &a_, &ir_.bytes.high}),
/* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(bc_.bytes.low),
@ -472,7 +472,7 @@ template <class T> class Processor {
/* 0x4c NEG */ StdInstr({MicroOp::NEG}), /* 0x4d RETI */ StdInstr(Pop(pc_), {MicroOp::RETN}),
/* 0x4e IM 0/1 */ StdInstr({MicroOp::IM}), /* 0x4f LD R, A */ Instr(3, {MicroOp::Move8, &a_, &ir_.bytes.low}),
/* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(de_.bytes.high),
/* 0x52 SBC HL, DE */ SBC16(hl_, de_), /* 0x53 LD (nn), DE */ StdInstr(Read16Inc(pc_, temp16_), Write16(temp16_, de_)),
/* 0x52 SBC HL, DE */ SBC16(hl_, de_), /* 0x53 LD (nn), DE */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, de_)),
/* 0x54 NEG */ StdInstr({MicroOp::NEG}), /* 0x55 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
/* 0x56 IM 1 */ StdInstr({MicroOp::IM}), /* 0x57 LD A, I */ Instr(3, {MicroOp::Move8, &ir_.bytes.high, &a_}, {MicroOp::SetAFlags}),
/* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(de_.bytes.low),
@ -480,7 +480,7 @@ template <class T> class Processor {
/* 0x5c NEG */ StdInstr({MicroOp::NEG}), /* 0x5d RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
/* 0x5e IM 2 */ StdInstr({MicroOp::IM}), /* 0x5f LD A, R */ Instr(3, {MicroOp::Move8, &ir_.bytes.low, &a_}, {MicroOp::SetAFlags}),
/* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(hl_.bytes.high),
/* 0x62 SBC HL, HL */ SBC16(hl_, hl_), /* 0x63 LD (nn), HL */ StdInstr(Read16Inc(pc_, temp16_), Write16(temp16_, hl_)),
/* 0x62 SBC HL, HL */ SBC16(hl_, hl_), /* 0x63 LD (nn), HL */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, hl_)),
/* 0x64 NEG */ StdInstr({MicroOp::NEG}), /* 0x65 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
/* 0x66 IM 0 */ StdInstr({MicroOp::IM}), /* 0x67 RRD */ StdInstr(Read3(hl_, temp8_), InternalOperation(4), {MicroOp::RRD}, Write3(hl_, temp8_)),
/* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(hl_.bytes.low),
@ -488,7 +488,7 @@ template <class T> class Processor {
/* 0x6c NEG */ StdInstr({MicroOp::NEG}), /* 0x6d RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
/* 0x6e IM 0/1 */ StdInstr({MicroOp::IM}), /* 0x6f RLD */ StdInstr(Read3(hl_, temp8_), InternalOperation(4), {MicroOp::RLD}, Write3(hl_, temp8_)),
/* 0x70 IN (C) */ IN_C(temp8_), /* 0x71 OUT (C), 0 */ StdInstr({MicroOp::SetZero}, Output(bc_, temp8_)),
/* 0x72 SBC HL, SP */ SBC16(hl_, sp_), /* 0x73 LD (nn), SP */ StdInstr(Read16Inc(pc_, temp16_), Write16(temp16_, sp_)),
/* 0x72 SBC HL, SP */ SBC16(hl_, sp_), /* 0x73 LD (nn), SP */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, sp_)),
/* 0x74 NEG */ StdInstr({MicroOp::NEG}), /* 0x75 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
/* 0x76 IM 1 */ StdInstr({MicroOp::IM}), /* 0x77 XX */ NOP,
/* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(a_),
@ -597,7 +597,7 @@ template <class T> class Processor {
/* 0x1f RRA */ StdInstr({MicroOp::RRA}),
/* 0x20 JR NZ */ JR(TestNZ), /* 0x21 LD HL, nn */ StdInstr(Read16Inc(pc_, index)),
/* 0x22 LD (nn), HL */ StdInstr(Read16Inc(pc_, temp16_), Write16(temp16_, index)),
/* 0x22 LD (nn), HL */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, index)),
/* 0x23 INC HL; 0x24 INC H; 0x25 DEC H; 0x26 LD H, n */
INC_INC_DEC_LD(index, index.bytes.high),