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Got to a parsing and towards an attempt to run FUSE tests.

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This commit is contained in:
Thomas Harte 2017-05-22 19:14:46 -04:00
parent 3fb3cc8269
commit 22afa509ca
4 changed files with 127 additions and 11 deletions
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14
OSBindings/Mac/Clock SignalTests/Bridges/TestMachineZ80.h
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@ -12,9 +12,17 @@ typedef NS_ENUM(NSInteger, CSTestMachineZ80Register) {
CSTestMachineZ80RegisterProgramCounter, CSTestMachineZ80RegisterProgramCounter,
CSTestMachineZ80RegisterStackPointer, CSTestMachineZ80RegisterStackPointer,
CSTestMachineZ80RegisterC, CSTestMachineZ80RegisterA, CSTestMachineZ80RegisterF, CSTestMachineZ80RegisterAF,
CSTestMachineZ80RegisterE, CSTestMachineZ80RegisterB, CSTestMachineZ80RegisterC, CSTestMachineZ80RegisterBC,
CSTestMachineZ80RegisterDE, CSTestMachineZ80RegisterD, CSTestMachineZ80RegisterE, CSTestMachineZ80RegisterDE,
CSTestMachineZ80RegisterH, CSTestMachineZ80RegisterL, CSTestMachineZ80RegisterHL,
CSTestMachineZ80RegisterAFDash,
CSTestMachineZ80RegisterBCDash,
CSTestMachineZ80RegisterDEDash,
CSTestMachineZ80RegisterHLDash,
CSTestMachineZ80RegisterIX, CSTestMachineZ80RegisterIY,
CSTestMachineZ80RegisterI, CSTestMachineZ80RegisterR,
CSTestMachineZ80RegisterIFF1, CSTestMachineZ80RegisterIFF2, CSTestMachineZ80RegisterIM
}; };
@class CSTestMachineZ80; @class CSTestMachineZ80;

31
OSBindings/Mac/Clock SignalTests/Bridges/TestMachineZ80.mm
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@ -31,11 +31,36 @@ class MachineTrapHandler: public CPU::AllRAMProcessor::TrapHandler {
static CPU::Z80::Register registerForRegister(CSTestMachineZ80Register reg) { static CPU::Z80::Register registerForRegister(CSTestMachineZ80Register reg) {
switch (reg) { switch (reg) {
case CSTestMachineZ80RegisterAF: return CPU::Z80::Register::AF;
case CSTestMachineZ80RegisterA: return CPU::Z80::Register::A;
case CSTestMachineZ80RegisterF: return CPU::Z80::Register::Flags;
case CSTestMachineZ80RegisterBC: return CPU::Z80::Register::BC;
case CSTestMachineZ80RegisterB: return CPU::Z80::Register::B;
case CSTestMachineZ80RegisterC: return CPU::Z80::Register::C;
case CSTestMachineZ80RegisterDE: return CPU::Z80::Register::DE;
case CSTestMachineZ80RegisterD: return CPU::Z80::Register::D;
case CSTestMachineZ80RegisterE: return CPU::Z80::Register::E;
case CSTestMachineZ80RegisterHL: return CPU::Z80::Register::HL;
case CSTestMachineZ80RegisterH: return CPU::Z80::Register::H;
case CSTestMachineZ80RegisterL: return CPU::Z80::Register::L;
case CSTestMachineZ80RegisterAFDash: return CPU::Z80::Register::AFDash;
case CSTestMachineZ80RegisterBCDash: return CPU::Z80::Register::BCDash;
case CSTestMachineZ80RegisterDEDash: return CPU::Z80::Register::DEDash;
case CSTestMachineZ80RegisterHLDash: return CPU::Z80::Register::HLDash;
case CSTestMachineZ80RegisterIX: return CPU::Z80::Register::IX;
case CSTestMachineZ80RegisterIY: return CPU::Z80::Register::IY;
case CSTestMachineZ80RegisterI: return CPU::Z80::Register::I;
case CSTestMachineZ80RegisterR: return CPU::Z80::Register::R;
case CSTestMachineZ80RegisterIFF1: return CPU::Z80::Register::IFF1;
case CSTestMachineZ80RegisterIFF2: return CPU::Z80::Register::IFF2;
case CSTestMachineZ80RegisterIM: return CPU::Z80::Register::IM;
case CSTestMachineZ80RegisterProgramCounter: return CPU::Z80::Register::ProgramCounter; case CSTestMachineZ80RegisterProgramCounter: return CPU::Z80::Register::ProgramCounter;
case CSTestMachineZ80RegisterStackPointer: return CPU::Z80::Register::StackPointer; case CSTestMachineZ80RegisterStackPointer: return CPU::Z80::Register::StackPointer;
case CSTestMachineZ80RegisterC: return CPU::Z80::Register::C;
case CSTestMachineZ80RegisterE: return CPU::Z80::Register::E;
case CSTestMachineZ80RegisterDE: return CPU::Z80::Register::DE;
} }
} }

78
OSBindings/Mac/Clock SignalTests/FUSETests.swift
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@ -17,14 +17,86 @@ class FUSETests: XCTestCase {
if let input = try? String(contentsOf: URL(fileURLWithPath: inputFilename), encoding: .utf8), if let input = try? String(contentsOf: URL(fileURLWithPath: inputFilename), encoding: .utf8),
let output = try? String(contentsOf: URL(fileURLWithPath: outputFilename), encoding: .utf8) { let output = try? String(contentsOf: URL(fileURLWithPath: outputFilename), encoding: .utf8) {
let inputScanner = Scanner(string: input)
let outputScanner = Scanner(string: output)
while !inputScanner.isAtEnd {
var name: NSString?
inputScanner.scanUpToCharacters(from: CharacterSet.newlines, into: &name)
if let name = name {
let machine = CSTestMachineZ80() let machine = CSTestMachineZ80()
// machine.setData(testData, atAddress: 0x0100)
// machine.setValue(0x0100, for: .programCounter) var af: UInt32 = 0, bc: UInt32 = 0, de: UInt32 = 0, hl: UInt32 = 0
var afDash: UInt32 = 0, bcDash: UInt32 = 0, deDash: UInt32 = 0, hlDash: UInt32 = 0
var ix: UInt32 = 0, iy: UInt32 = 0, sp: UInt32 = 0, pc: UInt32 = 0
var i: UInt32 = 0, r: UInt32 = 0, iff1: UInt32 = 0, iff2: UInt32 = 0, interruptMode: UInt32 = 0
var isHalted: UInt32 = 0, tStates: UInt32 = 0
// machine.runForNumber(ofCycles: 20) inputScanner.scanHexInt32(&af)
inputScanner.scanHexInt32(&bc)
inputScanner.scanHexInt32(&de)
inputScanner.scanHexInt32(&hl)
inputScanner.scanHexInt32(&afDash)
inputScanner.scanHexInt32(&bcDash)
inputScanner.scanHexInt32(&deDash)
inputScanner.scanHexInt32(&hlDash)
inputScanner.scanHexInt32(&ix)
inputScanner.scanHexInt32(&iy)
inputScanner.scanHexInt32(&sp)
inputScanner.scanHexInt32(&pc)
inputScanner.scanHexInt32(&i)
inputScanner.scanHexInt32(&r)
inputScanner.scanHexInt32(&iff1)
inputScanner.scanHexInt32(&iff2)
inputScanner.scanHexInt32(&interruptMode)
inputScanner.scanHexInt32(&isHalted)
inputScanner.scanHexInt32(&tStates)
print("\(name)")
machine.setValue(UInt16(af), for: .AF)
machine.setValue(UInt16(bc), for: .BC)
machine.setValue(UInt16(de), for: .DE)
machine.setValue(UInt16(hl), for: .HL)
machine.setValue(UInt16(afDash), for: .afDash)
machine.setValue(UInt16(bcDash), for: .bcDash)
machine.setValue(UInt16(deDash), for: .deDash)
machine.setValue(UInt16(hlDash), for: .hlDash)
machine.setValue(UInt16(ix), for: .IX)
machine.setValue(UInt16(iy), for: .IY)
machine.setValue(UInt16(sp), for: .stackPointer)
machine.setValue(UInt16(pc), for: .programCounter)
machine.setValue(UInt16(i), for: .I)
machine.setValue(UInt16(r), for: .R)
machine.setValue(UInt16(iff1), for: .IFF1)
machine.setValue(UInt16(iff2), for: .IFF2)
machine.setValue(UInt16(interruptMode), for: .IM)
// TODO: isHalted
while true {
var address: UInt32 = 0
var negative: Int = 0
if inputScanner.scanHexInt32(&address) {
while true {
var value: UInt32 = 0
if inputScanner.scanHexInt32(&value) {
machine.setValue(UInt8(value), atAddress: UInt16(address))
address = address + 1
} else {
inputScanner.scanInt(&negative)
break
} }
} }
} else {
inputScanner.scanInt(&negative)
break
}
} }
// machine.runForNumber(ofCycles: Int32(tStates))
}
}
}
}
}
} }

11
Processors/Z80/Z80.hpp
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@ -39,6 +39,8 @@ enum Register {
IXh, IXl, IX, IXh, IXl, IX,
IYh, IYl, IY, IYh, IYl, IY,
R, I, R, I,
IFF1, IFF2, IM
}; };
/* /*
@ -149,6 +151,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
RegisterPair afDash_, bcDash_, deDash_, hlDash_; RegisterPair afDash_, bcDash_, deDash_, hlDash_;
RegisterPair ix_, iy_, pc_, sp_; RegisterPair ix_, iy_, pc_, sp_;
bool iff1_, iff2_; bool iff1_, iff2_;
int interrupt_mode_;
uint8_t sign_result_, zero_result_, bit5_result_, half_carry_flag_, bit3_result_, parity_overflow_flag_, subtract_flag_, carry_flag_; uint8_t sign_result_, zero_result_, bit5_result_, half_carry_flag_, bit3_result_, parity_overflow_flag_, subtract_flag_, carry_flag_;
int number_of_cycles_; int number_of_cycles_;
@ -981,6 +984,10 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
case Register::R: return r_; case Register::R: return r_;
case Register::I: return i_; case Register::I: return i_;
case Register::IFF1: return iff1_ ? 1 : 0;
case Register::IFF2: return iff2_ ? 1 : 0;
case Register::IM: return interrupt_mode_;
default: return 0; default: return 0;
} }
} }
@ -1035,6 +1042,10 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
case Register::R: r_ = (uint8_t)value; break; case Register::R: r_ = (uint8_t)value; break;
case Register::I: i_ = (uint8_t)value; break; case Register::I: i_ = (uint8_t)value; break;
case Register::IFF1: iff1_ = !!value; break;
case Register::IFF2: iff2_ = !!value; break;
case Register::IM: interrupt_mode_ = value % 2; break;
default: break; default: break;
} }
} }