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Decodes operations for the simplest 45.
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Thomas Harte
parent
ed63e7ea75
commit
233a69a1d8
@ -13,162 +13,70 @@ using namespace CPU::Decoder::PowerPC;
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Decoder::Decoder(Model model) : model_(model) {}
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Instruction Decoder::decode(uint32_t opcode) {
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switch(opcode >> 26) {
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case 31:
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const uint8_t dest = (opcode >> 21) & 0x1f;
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const uint8_t a = (opcode >> 16) & 0x1f;
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const uint8_t b = (opcode >> 11) & 0x1f;
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// Quick bluffer's guide to PowerPC instruction encoding:
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//
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// There is a six-bit field at the very top of the instruction.
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// Sometimes that fully identifies an instruction, but usually
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// it doesn't.
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//
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// There is an addition 9- or 10-bit field starting one bit above
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// least significant that disambiguates the rest. Strictly speaking
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// it's a 10-bit field, but the mnemonics for many instructions treat
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// it as a 9-bit field with a flag at the top.
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//
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// I've decided to hew directly to the mnemonics.
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#define OECase(x) case x: case 0x200 + x
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switch((opcode >> 1) & 0x3ff) {
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case 0:
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// cmp; 601 10-26
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break;
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case 4:
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// tw; 601 10-214
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break;
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OECase(8):
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// subfcx; 601 10-207
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break;
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// case 9:
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// // mulhdux
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// break;
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OECase(10):
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// addcx; 601 10-9
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break;
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case 11:
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// mulhwux; 601 10-142
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break;
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case 19:
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// mfcr; 601 10-122
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break;
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case 20:
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// lwarx
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break;
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case 21:
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// ldx
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break;
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// lwzx
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// slwx
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// cntlzwx
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// sldx
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// andx
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// ampl
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// subfx
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// ldux
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// dcbst
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// lwzux
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// cntlzdx
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// andcx
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// td
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// mulhx
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// mulhwx
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// mfmsr
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// ldarx
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// dcbf
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// lbzx
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// negx
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// norx
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// subfex
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// adex
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// mtcrf
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// mtmsr
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// stfx
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// stwcx.
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// stwx
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// stdux
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// stwux
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// subfzex
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// addzex
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// mtsr
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// stdcx.
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// stbx
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// subfmex
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// mulld
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// addmex
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// mullwx
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// mtsrin
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// scbtst
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// stbux
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// addx
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// dcbt
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// lhzx
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// eqvx
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// tlbie
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// eciwx
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// lhzux
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// xorx
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// mfspr
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// lwax
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// lhax
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// lbia
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// mftb
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// lwaux
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// lhaux
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// sthx
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// orcx
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// sradix
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// slbie
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// ecowx
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// sthux
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// orx
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// divdux
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// divwux
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// mtspr
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// dcbi
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// nandx
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// divdx
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// divwx
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// slbia
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// mcrxr
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// lswx
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// lwbrx
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// lfsx
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// srwx
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// srdx
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// tlbsync
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// lfsux
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// mfsr
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// lswi
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// sync
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// lfdx
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// lfdux
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// mfsrin
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// stswx
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// stwbrx
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// stfsx
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// stfsux
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// stswi
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// stfdx
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// stfdux
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// lhbrx
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// srawx
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// sradx
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// srawix
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// eieio
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// ethbrx
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// extshx
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// extsbx
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// lcbi
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// stfiwx
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// extsw
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// dcbz
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OECase(138):
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// addex
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break;
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OECase(266):
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// addx
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break;
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case 28:
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// andx
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break;
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case 60:
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// andcx
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break;
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}
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#undef OECase
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break;
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#define Bind(mask, operation) case mask: return Instruction(Operation::operation, opcode);
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#define BindConditional(condition, mask, operation) \
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case mask: \
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if(condition()) return Instruction(Operation::operation, opcode); \
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return Instruction(opcode);
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#define Six(x) (unsigned(x) << 26)
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// First pass: weed out all those instructions identified entirely by the
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// top six bits.
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switch(opcode & Six(0b111111)) {
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default: break;
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BindConditional(is64bit, Six(0b000010), tdi);
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Bind(Six(0b000011), twi);
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Bind(Six(0b000111), mulli);
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Bind(Six(0b001000), subfic);
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Bind(Six(0b001100), addic); Bind(Six(0b001101), addic_);
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Bind(Six(0b001110), addi); Bind(Six(0b001111), addis);
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Bind(Six(0b010000), bcx);
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Bind(Six(0b010010), bx);
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Bind(Six(0b010100), rlwimix);
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Bind(Six(0b010101), rlwinmx);
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Bind(Six(0b010111), rlwnmx);
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Bind(Six(0b011000), ori); Bind(Six(0b011001), oris);
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Bind(Six(0b011010), xori); Bind(Six(0b011011), xoris);
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Bind(Six(0b011100), andi_); Bind(Six(0b011101), andis_);
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Bind(Six(0b100000), lwz); Bind(Six(0b100001), lwzu);
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Bind(Six(0b100010), lbz); Bind(Six(0b100011), lbzu);
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Bind(Six(0b100100), stw); Bind(Six(0b100101), stwu);
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Bind(Six(0b100110), stb); Bind(Six(0b100111), stbu);
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Bind(Six(0b101000), lhz); Bind(Six(0b101001), lhzu);
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Bind(Six(0b101010), lha); Bind(Six(0b101011), lhau);
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Bind(Six(0b101100), sth); Bind(Six(0b101101), sthu);
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Bind(Six(0b101110), lmw); Bind(Six(0b101111), stmw);
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Bind(Six(0b110000), lfs); Bind(Six(0b110001), lfsu);
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Bind(Six(0b110010), lfd); Bind(Six(0b110011), lfdu);
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Bind(Six(0b110100), stfs); Bind(Six(0b110101), stfsu);
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Bind(Six(0b110110), stfd); Bind(Six(0b110111), stfdu);
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// Assumed below here: reserved bits can be ignored.
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// This might need to be a function of CPU model.
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Bind(Six(0b001010), cmpli); Bind(Six(0b001011), cmpi);
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}
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return Instruction();
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#undef Six
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#undef Bind
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#undef BindConditional
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return Instruction(opcode);
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}
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@ -55,16 +55,17 @@ enum class Operation: uint8_t {
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fresx, frsqrtex, fselx, fsqrtx, frsqrtsx, slbia, slbie,
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// 64-bit only PowerPC instructions.
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cntlzdx, divdx, divdux, extswx, fcfidx, fctidx, fctidzx
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cntlzdx, divdx, divdux, extswx, fcfidx, fctidx, fctidzx, tdi
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};
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struct Instruction {
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Operation operation = Operation::Undefined;
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const Operation operation = Operation::Undefined;
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const uint32_t opcode = 0;
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//
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Instruction(uint32_t opcode) : opcode(opcode) {}
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Instruction(Operation operation, uint32_t opcode) : operation(operation), opcode(opcode) {}
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Instruction() {}
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Instruction(Operation operation) : operation(operation) {}
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// TODO: all field decoding here.
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};
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struct Decoder {
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@ -75,6 +76,14 @@ struct Decoder {
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private:
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Model model_;
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bool is64bit() {
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return false;
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}
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bool is601() {
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return model_ == Model::MPC601;
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}
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};
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}
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