mirror of
https://github.com/TomHarte/CLK.git
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Merge pull request #154 from TomHarte/Memptr
Introduces a subset of necessary test cases for the Z80 memptr register, and corrects implementation to match
This commit is contained in:
Thomas Harte
GitHub
commit
25fd95044c
@ -13,6 +13,8 @@
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#include <typeinfo>
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#include <cstdio>
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#include "../../ClockReceiver/ClockReceiver.hpp"
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namespace MOS {
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/*!
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@ -12,6 +12,8 @@
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#include <cstdint>
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#include <cstdio>
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#include "../../ClockReceiver/ClockReceiver.hpp"
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namespace MOS {
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/*!
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@ -7,6 +7,7 @@
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objects = {
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/* Begin PBXBuildFile section */
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4B01A6881F22F0DB001FD6E3 /* Z80MemptrTests.swift in Sources */ = {isa = PBXBuildFile; fileRef = 4B01A6871F22F0DB001FD6E3 /* Z80MemptrTests.swift */; };
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4B049CDD1DA3C82F00322067 /* BCDTest.swift in Sources */ = {isa = PBXBuildFile; fileRef = 4B049CDC1DA3C82F00322067 /* BCDTest.swift */; };
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4B08A2751EE35D56008B7065 /* Z80InterruptTests.swift in Sources */ = {isa = PBXBuildFile; fileRef = 4B08A2741EE35D56008B7065 /* Z80InterruptTests.swift */; };
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4B08A2781EE39306008B7065 /* TestMachine.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4B08A2771EE39306008B7065 /* TestMachine.mm */; };
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@ -456,6 +457,7 @@
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/* End PBXContainerItemProxy section */
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/* Begin PBXFileReference section */
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4B01A6871F22F0DB001FD6E3 /* Z80MemptrTests.swift */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.swift; path = Z80MemptrTests.swift; sourceTree = "<group>"; };
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4B046DC31CFE651500E9E45E /* CRTMachine.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = CRTMachine.hpp; sourceTree = "<group>"; };
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4B049CDC1DA3C82F00322067 /* BCDTest.swift */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.swift; path = BCDTest.swift; sourceTree = "<group>"; };
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4B08A2741EE35D56008B7065 /* Z80InterruptTests.swift */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.swift; path = Z80InterruptTests.swift; sourceTree = "<group>"; };
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@ -1882,6 +1884,7 @@
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4B14145F1B58885000E04248 /* WolfgangLorenzTests.swift */,
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4B08A2741EE35D56008B7065 /* Z80InterruptTests.swift */,
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4BDDBA981EF3451200347E61 /* Z80MachineCycleTests.swift */,
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4B01A6871F22F0DB001FD6E3 /* Z80MemptrTests.swift */,
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4BFCA12A1ECBE7C400AC40C1 /* ZexallTests.swift */,
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4B3BA0C41D318B44005DD7A7 /* Bridges */,
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4B1414631B588A1100E04248 /* Test Binaries */,
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@ -2720,6 +2723,7 @@
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4B92EACA1B7C112B00246143 /* 6502TimingTests.swift in Sources */,
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4BFCA1201ECBDC1500AC40C1 /* Z80AllRAM.cpp in Sources */,
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4BB73EB71B587A5100552FC2 /* AllSuiteATests.swift in Sources */,
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4B01A6881F22F0DB001FD6E3 /* Z80MemptrTests.swift in Sources */,
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4B121F9B1E06293F00BFDA12 /* PCMSegmentEventSourceTests.mm in Sources */,
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4BEF6AAC1D35D1C400E73575 /* DPLLTests.swift in Sources */,
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4B3BA0CF1D318B44005DD7A7 /* MOS6522Bridge.mm in Sources */,
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@ -42,7 +42,8 @@ typedef NS_ENUM(NSInteger, CSTestMachineZ80Register) {
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CSTestMachineZ80RegisterHLDash,
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CSTestMachineZ80RegisterIX, CSTestMachineZ80RegisterIY,
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CSTestMachineZ80RegisterI, CSTestMachineZ80RegisterR,
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CSTestMachineZ80RegisterIFF1, CSTestMachineZ80RegisterIFF2, CSTestMachineZ80RegisterIM
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CSTestMachineZ80RegisterIFF1, CSTestMachineZ80RegisterIFF2, CSTestMachineZ80RegisterIM,
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CSTestMachineZ80RegisterMemPtr
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};
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@interface CSTestMachineZ80 : CSTestMachine
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@ -65,6 +65,8 @@ static CPU::Z80::Register registerForRegister(CSTestMachineZ80Register reg) {
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case CSTestMachineZ80RegisterProgramCounter: return CPU::Z80::Register::ProgramCounter;
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case CSTestMachineZ80RegisterStackPointer: return CPU::Z80::Register::StackPointer;
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case CSTestMachineZ80RegisterMemPtr: return CPU::Z80::Register::MemPtr;
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}
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}
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348
OSBindings/Mac/Clock SignalTests/Z80MemptrTests.swift
Normal file
348
OSBindings/Mac/Clock SignalTests/Z80MemptrTests.swift
Normal file
@ -0,0 +1,348 @@
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//
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// Z80MemptrTests.swift
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// Clock Signal
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//
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// Created by Thomas Harte on 21/07/2017.
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// Copyright © 2017 Thomas Harte. All rights reserved.
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//
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import XCTest
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class Z80MemptrTests: XCTestCase {
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private let machine = CSTestMachineZ80()
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private func test(program : [UInt8], length : Int32, initialValue : UInt16) -> UInt16 {
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// Create a machine and install the supplied program at address 0, setting the PC to run from there
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machine.setValue(0x0000, for: .programCounter)
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machine.setData(Data(bytes: program), atAddress: 0x0000)
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// Set the initial value of memptr, run for the requested number of cycles,
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// return the new value
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machine.setValue(initialValue, for: .memPtr)
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machine.runForNumber(ofCycles: length)
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return machine.value(for: .memPtr)
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}
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// LD A, (addr)
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func testLDAnn() {
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// MEMPTR = addr+1
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var program: [UInt8] = [
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0x3a, 0x00, 0x00
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]
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for addr in 0 ..< 65536 {
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program[1] = UInt8(addr & 0x00ff)
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program[2] = UInt8(addr >> 8)
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let expectedResult = UInt16((addr + 1) & 0xffff)
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let result = test(program: program, length: 13, initialValue: 0xffff)
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XCTAssertEqual(result, expectedResult)
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}
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}
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/* TODO:
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LD (addr),A
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MEMPTR_low = (addr + 1) & #FF, MEMPTR_hi = A
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Note for *BM1: MEMPTR_low = (addr + 1) & #FF, MEMPTR_hi = 0
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*/
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// LD A, (rp)
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func testLDArp() {
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// MEMPTR = rp+1
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let bcProgram: [UInt8] = [
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0x0a
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]
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let deProgram: [UInt8] = [
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0x1a
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]
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for addr in 0 ..< 65536 {
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machine.setValue(UInt16(addr), for: .BC)
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machine.setValue(UInt16(addr), for: .DE)
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let expectedResult = UInt16((addr + 1) & 0xffff)
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let bcResult = test(program: bcProgram, length: 7, initialValue: 0xffff)
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let deResult = test(program: deProgram, length: 7, initialValue: 0xffff)
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XCTAssertEqual(bcResult, expectedResult)
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XCTAssertEqual(deResult, expectedResult)
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}
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}
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/* TODO:
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LD (rp),A where rp -- BC or DE
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MEMPTR_low = (rp + 1) & #FF, MEMPTR_hi = A
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Note for *BM1: MEMPTR_low = (rp + 1) & #FF, MEMPTR_hi = 0
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*/
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/* TODO:
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LD (addr), rp
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MEMPTR = addr + 1
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*/
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// LD rp, (addr)
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func testLDnnrp() {
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// MEMPTR = addr+1
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var hlBaseProgram: [UInt8] = [
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0x22, 0x00, 0x00
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]
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var bcEDProgram: [UInt8] = [
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0xed, 0x43, 0x00, 0x00
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]
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var deEDProgram: [UInt8] = [
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0xed, 0x53, 0x00, 0x00
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]
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var hlEDProgram: [UInt8] = [
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0xed, 0x63, 0x00, 0x00
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]
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var spEDProgram: [UInt8] = [
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0xed, 0x73, 0x00, 0x00
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]
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var ixProgram: [UInt8] = [
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0xdd, 0x22, 0x00, 0x00
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]
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var iyProgram: [UInt8] = [
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0xfd, 0x22, 0x00, 0x00
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]
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for addr in 0 ..< 65536 {
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hlBaseProgram[1] = UInt8(addr & 0x00ff)
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hlBaseProgram[2] = UInt8(addr >> 8)
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bcEDProgram[2] = UInt8(addr & 0x00ff)
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bcEDProgram[3] = UInt8(addr >> 8)
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deEDProgram[2] = UInt8(addr & 0x00ff)
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deEDProgram[3] = UInt8(addr >> 8)
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hlEDProgram[2] = UInt8(addr & 0x00ff)
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hlEDProgram[3] = UInt8(addr >> 8)
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spEDProgram[2] = UInt8(addr & 0x00ff)
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spEDProgram[3] = UInt8(addr >> 8)
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ixProgram[2] = UInt8(addr & 0x00ff)
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ixProgram[3] = UInt8(addr >> 8)
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iyProgram[2] = UInt8(addr & 0x00ff)
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iyProgram[3] = UInt8(addr >> 8)
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let expectedResult = UInt16((addr + 1) & 0xffff)
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XCTAssertEqual(test(program: hlBaseProgram, length: 16, initialValue: 0xffff), expectedResult)
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XCTAssertEqual(test(program: bcEDProgram, length: 20, initialValue: 0xffff), expectedResult)
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XCTAssertEqual(test(program: deEDProgram, length: 20, initialValue: 0xffff), expectedResult)
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XCTAssertEqual(test(program: hlEDProgram, length: 20, initialValue: 0xffff), expectedResult)
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XCTAssertEqual(test(program: spEDProgram, length: 20, initialValue: 0xffff), expectedResult)
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XCTAssertEqual(test(program: ixProgram, length: 20, initialValue: 0xffff), expectedResult)
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XCTAssertEqual(test(program: iyProgram, length: 20, initialValue: 0xffff), expectedResult)
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}
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}
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// EX (SP), rp
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func testEXSPrp() {
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// MEMPTR = rp at end
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var hlProgram: [UInt8] = [
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0xe3, 0x00, 0x00, 0x00
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]
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var ixProgram: [UInt8] = [
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0xdd, 0xe3, 0x00, 0x00
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]
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var iyProgram: [UInt8] = [
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0xfd, 0xe3, 0x00, 0x00
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]
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machine.setValue(2, for: .stackPointer)
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for addr in 0 ..< 65536 {
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hlProgram[2] = UInt8(addr & 0x00ff)
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hlProgram[3] = UInt8(addr >> 8)
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ixProgram[2] = UInt8(addr & 0x00ff)
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ixProgram[3] = UInt8(addr >> 8)
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iyProgram[2] = UInt8(addr & 0x00ff)
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iyProgram[3] = UInt8(addr >> 8)
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XCTAssertEqual(test(program: hlProgram, length: 19, initialValue: 0xffff), UInt16(addr))
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XCTAssertEqual(test(program: ixProgram, length: 23, initialValue: 0xffff), UInt16(addr))
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XCTAssertEqual(test(program: iyProgram, length: 23, initialValue: 0xffff), UInt16(addr))
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}
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}
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// ADD/ADC/SBC dest, src
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func testADDADCSBCrr() {
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// MEMPTR = dest prior to modification + 1
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let addProgram: [UInt8] = [
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0x09
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]
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let adcProgram: [UInt8] = [
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0xed, 0x4a
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]
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let sbcProgram: [UInt8] = [
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0xed, 0x42
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]
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for addr in 0 ..< 65536 {
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let expectedResult = UInt16((addr + 1) & 0xffff)
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machine.setValue(UInt16(addr), for: .HL)
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XCTAssertEqual(test(program: addProgram, length: 11, initialValue: 0xffff), expectedResult)
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XCTAssertEqual(test(program: adcProgram, length: 15, initialValue: 0xffff), expectedResult)
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XCTAssertEqual(test(program: sbcProgram, length: 15, initialValue: 0xffff), expectedResult)
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}
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}
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// RLD/RRD
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func testRLDRRD() {
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// MEMPTR = HL + 1
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let rldProgram: [UInt8] = [
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0xed, 0x6f
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]
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let rrdProgram: [UInt8] = [
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0xed, 0x67
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]
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for addr in 0 ..< 65536 {
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let expectedResult = UInt16((addr + 1) & 0xffff)
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machine.setValue(UInt16(addr), for: .HL)
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XCTAssertEqual(test(program: rldProgram, length: 18, initialValue: 0xffff), expectedResult)
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XCTAssertEqual(test(program: rrdProgram, length: 18, initialValue: 0xffff), expectedResult)
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}
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}
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/* TODO:
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JR/DJNZ/RET/RETI/RST (jumping to addr)
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MEMPTR = addr
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*/
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/* TODO:
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JP(except JP rp)/CALL addr (even in case of conditional call/jp, independantly on condition satisfied or not)
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MEMPTR = addr
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*/
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/* TODO:
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IN A,(port)
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MEMPTR = (A_before_operation << 8) + port + 1
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*/
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/* TODO:
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IN A,(C)
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MEMPTR = BC + 1
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*/
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/* TODO:
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OUT (port),A
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MEMPTR_low = (port + 1) & #FF, MEMPTR_hi = A
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Note for *BM1: MEMPTR_low = (port + 1) & #FF, MEMPTR_hi = 0
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*/
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/* TODO:
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OUT (C),A
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MEMPTR = BC + 1
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*/
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/* TODO:
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LDIR/LDDR
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when BC == 1: MEMPTR is not changed
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when BC <> 1: MEMPTR = PC + 1, where PC = instruction address
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*/
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// CPI
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func testCPI() {
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// MEMPTR = MEMPTR + 1
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let program: [UInt8] = [
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0xed, 0xa1
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]
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machine.setData(Data(bytes: program), atAddress: 0x0000)
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machine.setValue(0, for: .memPtr)
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for c in 1 ..< 65536 {
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machine.setValue(0x0000, for: .programCounter)
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machine.runForNumber(ofCycles: 16)
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XCTAssertEqual(UInt16(c), machine.value(for: .memPtr))
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}
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}
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// CPD
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func testCPD() {
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// MEMPTR = MEMPTR - 1
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let program: [UInt8] = [
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0xed, 0xa9
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]
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machine.setData(Data(bytes: program), atAddress: 0x0000)
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machine.setValue(0, for: .memPtr)
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for c in 1 ..< 65536 {
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machine.setValue(0x0000, for: .programCounter)
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machine.runForNumber(ofCycles: 16)
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XCTAssertEqual(UInt16(65536 - c), machine.value(for: .memPtr))
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}
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}
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/* TODO:
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CPIR
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when BC=1 or A=(HL): exactly as CPI
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In other cases MEMPTR = PC + 1 on each step, where PC = instruction address.
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Note* since at the last execution BC=1 or A=(HL), resulting MEMPTR = PC + 1 + 1
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(if there were not interrupts during the execution)
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*/
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/* TODO:
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CPDR
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when BC=1 or A=(HL): exactly as CPD
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In other cases MEMPTR = PC + 1 on each step, where PC = instruction address.
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Note* since at the last execution BC=1 or A=(HL), resulting MEMPTR = PC + 1 - 1
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(if there were not interrupts during the execution)
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*/
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/* TODO:
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INI
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MEMPTR = BC_before_decrementing_B + 1
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*/
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/* TODO:
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IND
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MEMPTR = BC_before_decrementing_B - 1
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*/
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/* TODO:
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INIR
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exactly as INI on each execution.
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I.e. resulting MEMPTR = ((1 << 8) + C) + 1
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*/
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/* TODO:
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INDR
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exactly as IND on each execution.
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I.e. resulting MEMPTR = ((1 << 8) + C) - 1
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*/
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/* TODO:
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OUTI
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MEMPTR = BC_after_decrementing_B + 1
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*/
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/* TODO:
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OUTD
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MEMPTR = BC_after_decrementing_B - 1
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*/
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/* TODO:
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OTIR
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exactly as OUTI on each execution. I.e. resulting MEMPTR = C + 1
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*/
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/* TODO:
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OTDR
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exactly as OUTD on each execution. I.e. resulting MEMPTR = C - 1
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*/
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/* TODO:
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Any instruction with (INDEX+d):
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MEMPTR = INDEX+d
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*/
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/* TODO:
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Interrupt call to addr:
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As usual CALL. I.e. MEMPTR = addr
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*/
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}
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@ -41,7 +41,9 @@ enum Register {
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IYh, IYl, IY,
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R, I, Refresh,
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IFF1, IFF2, IM
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IFF1, IFF2, IM,
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MemPtr
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};
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/*
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@ -463,7 +465,7 @@ template <class T> class Processor {
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NOP_ROW(), /* 0x20 */
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NOP_ROW(), /* 0x30 */
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/* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(bc_.bytes.high),
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/* 0x42 SBC HL, BC */ SBC16(hl_, bc_), /* 0x43 LD (nn), BC */ StdInstr(Read16Inc(pc_, temp16_), Write16(temp16_, bc_)),
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/* 0x42 SBC HL, BC */ SBC16(hl_, bc_), /* 0x43 LD (nn), BC */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, bc_)),
|
||||
/* 0x44 NEG */ StdInstr({MicroOp::NEG}), /* 0x45 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x46 IM 0 */ StdInstr({MicroOp::IM}), /* 0x47 LD I, A */ Instr(6, {MicroOp::Move8, &a_, &ir_.bytes.high}),
|
||||
/* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(bc_.bytes.low),
|
||||
@ -471,7 +473,7 @@ template <class T> class Processor {
|
||||
/* 0x4c NEG */ StdInstr({MicroOp::NEG}), /* 0x4d RETI */ StdInstr(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x4e IM 0/1 */ StdInstr({MicroOp::IM}), /* 0x4f LD R, A */ Instr(6, {MicroOp::Move8, &a_, &ir_.bytes.low}),
|
||||
/* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(de_.bytes.high),
|
||||
/* 0x52 SBC HL, DE */ SBC16(hl_, de_), /* 0x53 LD (nn), DE */ StdInstr(Read16Inc(pc_, temp16_), Write16(temp16_, de_)),
|
||||
/* 0x52 SBC HL, DE */ SBC16(hl_, de_), /* 0x53 LD (nn), DE */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, de_)),
|
||||
/* 0x54 NEG */ StdInstr({MicroOp::NEG}), /* 0x55 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x56 IM 1 */ StdInstr({MicroOp::IM}), /* 0x57 LD A, I */ Instr(6, {MicroOp::Move8, &ir_.bytes.high, &a_}, {MicroOp::SetAFlags}),
|
||||
/* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(de_.bytes.low),
|
||||
@ -479,7 +481,7 @@ template <class T> class Processor {
|
||||
/* 0x5c NEG */ StdInstr({MicroOp::NEG}), /* 0x5d RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x5e IM 2 */ StdInstr({MicroOp::IM}), /* 0x5f LD A, R */ Instr(6, {MicroOp::Move8, &ir_.bytes.low, &a_}, {MicroOp::SetAFlags}),
|
||||
/* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(hl_.bytes.high),
|
||||
/* 0x62 SBC HL, HL */ SBC16(hl_, hl_), /* 0x63 LD (nn), HL */ StdInstr(Read16Inc(pc_, temp16_), Write16(temp16_, hl_)),
|
||||
/* 0x62 SBC HL, HL */ SBC16(hl_, hl_), /* 0x63 LD (nn), HL */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, hl_)),
|
||||
/* 0x64 NEG */ StdInstr({MicroOp::NEG}), /* 0x65 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x66 IM 0 */ StdInstr({MicroOp::IM}), /* 0x67 RRD */ StdInstr(Read3(hl_, temp8_), InternalOperation(8), {MicroOp::RRD}, Write3(hl_, temp8_)),
|
||||
/* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(hl_.bytes.low),
|
||||
@ -487,7 +489,7 @@ template <class T> class Processor {
|
||||
/* 0x6c NEG */ StdInstr({MicroOp::NEG}), /* 0x6d RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x6e IM 0/1 */ StdInstr({MicroOp::IM}), /* 0x6f RLD */ StdInstr(Read3(hl_, temp8_), InternalOperation(8), {MicroOp::RLD}, Write3(hl_, temp8_)),
|
||||
/* 0x70 IN (C) */ IN_C(temp8_), /* 0x71 OUT (C), 0 */ StdInstr({MicroOp::SetZero}, Output(bc_, temp8_)),
|
||||
/* 0x72 SBC HL, SP */ SBC16(hl_, sp_), /* 0x73 LD (nn), SP */ StdInstr(Read16Inc(pc_, temp16_), Write16(temp16_, sp_)),
|
||||
/* 0x72 SBC HL, SP */ SBC16(hl_, sp_), /* 0x73 LD (nn), SP */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, sp_)),
|
||||
/* 0x74 NEG */ StdInstr({MicroOp::NEG}), /* 0x75 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x76 IM 1 */ StdInstr({MicroOp::IM}), /* 0x77 XX */ NOP,
|
||||
/* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(a_),
|
||||
@ -573,7 +575,7 @@ template <class T> class Processor {
|
||||
|
||||
/* 0x07 RLCA */ StdInstr({MicroOp::RLCA}),
|
||||
/* 0x08 EX AF, AF' */ StdInstr({MicroOp::ExAFAFDash}), /* 0x09 ADD HL, BC */ ADD16(index, bc_),
|
||||
/* 0x0a LD A, (BC) */ StdInstr({MicroOp::Move16, &bc_.full, &memptr_.full}, Read3(memptr_, a_)),
|
||||
/* 0x0a LD A, (BC) */ StdInstr({MicroOp::Move16, &bc_.full, &memptr_.full}, Read3(memptr_, a_), Inc16(memptr_)),
|
||||
|
||||
/* 0x0b DEC BC; 0x0c INC C; 0x0d DEC C; 0x0e LD C, n */
|
||||
DEC_INC_DEC_LD(bc_, bc_.bytes.low),
|
||||
@ -589,14 +591,14 @@ template <class T> class Processor {
|
||||
/* 0x17 RLA */ StdInstr({MicroOp::RLA}),
|
||||
/* 0x18 JR */ StdInstr(ReadInc(pc_, temp8_), InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}),
|
||||
/* 0x19 ADD HL, DE */ ADD16(index, de_),
|
||||
/* 0x1a LD A, (DE) */ StdInstr({MicroOp::Move16, &de_.full, &memptr_.full}, Read3(memptr_, a_)),
|
||||
/* 0x1a LD A, (DE) */ StdInstr({MicroOp::Move16, &de_.full, &memptr_.full}, Read3(memptr_, a_), Inc16(memptr_)),
|
||||
|
||||
/* 0x1b DEC DE; 0x1c INC E; 0x1d DEC E; 0x1e LD E, n */
|
||||
DEC_INC_DEC_LD(de_, de_.bytes.low),
|
||||
|
||||
/* 0x1f RRA */ StdInstr({MicroOp::RRA}),
|
||||
/* 0x20 JR NZ */ JR(TestNZ), /* 0x21 LD HL, nn */ StdInstr(Read16Inc(pc_, index)),
|
||||
/* 0x22 LD (nn), HL */ StdInstr(Read16Inc(pc_, temp16_), Write16(temp16_, index)),
|
||||
/* 0x22 LD (nn), HL */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, index)),
|
||||
|
||||
/* 0x23 INC HL; 0x24 INC H; 0x25 DEC H; 0x26 LD H, n */
|
||||
INC_INC_DEC_LD(index, index.bytes.high),
|
||||
@ -618,7 +620,7 @@ template <class T> class Processor {
|
||||
/* 0x37 SCF */ StdInstr({MicroOp::SCF}),
|
||||
/* 0x38 JR C */ JR(TestC),
|
||||
/* 0x39 ADD HL, SP */ ADD16(index, sp_),
|
||||
/* 0x3a LD A, (nn) */ StdInstr(Read16Inc(pc_, memptr_), Read3(memptr_, a_)),
|
||||
/* 0x3a LD A, (nn) */ StdInstr(Read16Inc(pc_, memptr_), Read3(memptr_, a_), Inc16(memptr_)),
|
||||
/* 0x3b DEC SP */ Instr(8, {MicroOp::Decrement16, &sp_.full}),
|
||||
|
||||
/* 0x3c INC A; 0x3d DEC A; 0x3e LD A, n */
|
||||
@ -1196,9 +1198,9 @@ template <class T> class Processor {
|
||||
#pragma mark - 16-bit arithmetic
|
||||
|
||||
case MicroOp::ADD16: {
|
||||
memptr_.full = *(uint16_t *)operation->source;
|
||||
uint16_t sourceValue = memptr_.full;
|
||||
uint16_t destinationValue = *(uint16_t *)operation->destination;
|
||||
memptr_.full = *(uint16_t *)operation->destination;
|
||||
uint16_t sourceValue = *(uint16_t *)operation->source;
|
||||
uint16_t destinationValue = memptr_.full;
|
||||
int result = sourceValue + destinationValue;
|
||||
int halfResult = (sourceValue&0xfff) + (destinationValue&0xfff);
|
||||
|
||||
@ -1208,12 +1210,13 @@ template <class T> class Processor {
|
||||
subtract_flag_ = 0;
|
||||
|
||||
*(uint16_t *)operation->destination = (uint16_t)result;
|
||||
memptr_.full++;
|
||||
} break;
|
||||
|
||||
case MicroOp::ADC16: {
|
||||
memptr_.full = *(uint16_t *)operation->source;
|
||||
uint16_t sourceValue = memptr_.full;
|
||||
uint16_t destinationValue = *(uint16_t *)operation->destination;
|
||||
memptr_.full = *(uint16_t *)operation->destination;
|
||||
uint16_t sourceValue = *(uint16_t *)operation->source;
|
||||
uint16_t destinationValue = memptr_.full;
|
||||
int result = sourceValue + destinationValue + (carry_result_ & Flag::Carry);
|
||||
int halfResult = (sourceValue&0xfff) + (destinationValue&0xfff) + (carry_result_ & Flag::Carry);
|
||||
|
||||
@ -1228,12 +1231,13 @@ template <class T> class Processor {
|
||||
parity_overflow_result_ = (uint8_t)(overflow >> 13);
|
||||
|
||||
*(uint16_t *)operation->destination = (uint16_t)result;
|
||||
memptr_.full++;
|
||||
} break;
|
||||
|
||||
case MicroOp::SBC16: {
|
||||
memptr_.full = *(uint16_t *)operation->source;
|
||||
uint16_t sourceValue = memptr_.full;
|
||||
uint16_t destinationValue = *(uint16_t *)operation->destination;
|
||||
memptr_.full = *(uint16_t *)operation->destination;
|
||||
uint16_t sourceValue = *(uint16_t *)operation->source;
|
||||
uint16_t destinationValue = memptr_.full;
|
||||
int result = destinationValue - sourceValue - (carry_result_ & Flag::Carry);
|
||||
int halfResult = (destinationValue&0xfff) - (sourceValue&0xfff) - (carry_result_ & Flag::Carry);
|
||||
|
||||
@ -1251,6 +1255,7 @@ template <class T> class Processor {
|
||||
parity_overflow_result_ = (uint8_t)(overflow >> 13);
|
||||
|
||||
*(uint16_t *)operation->destination = (uint16_t)result;
|
||||
memptr_.full++;
|
||||
} break;
|
||||
|
||||
#pragma mark - Conditionals
|
||||
@ -1796,6 +1801,8 @@ template <class T> class Processor {
|
||||
case Register::IFF2: return iff2_ ? 1 : 0;
|
||||
case Register::IM: return (uint16_t)interrupt_mode_;
|
||||
|
||||
case Register::MemPtr: return memptr_.full;
|
||||
|
||||
default: return 0;
|
||||
}
|
||||
}
|
||||
@ -1855,6 +1862,8 @@ template <class T> class Processor {
|
||||
case Register::IFF2: iff2_ = !!value; break;
|
||||
case Register::IM: interrupt_mode_ = value % 3; break;
|
||||
|
||||
case Register::MemPtr: memptr_.full = value; break;
|
||||
|
||||
default: break;
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user