From 274902c3c19555bb3c3f1166bbb52d0ba6225293 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Thu, 19 May 2022 11:23:26 -0400
Subject: [PATCH] Add to-memory write-back. Am going to reconsider usage of
 temporary_address_ as noted.

---
 .../Implementation/68000Mk2Implementation.hpp | 28 +++++++++++++++----
 1 file changed, 23 insertions(+), 5 deletions(-)

diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
index 1b4cbeb88..b3ce31921 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -29,6 +29,7 @@ enum ExecutionState: int {
 	FetchOperand_l,
 
 	StoreOperand,
+	StoreOperand_l,
 
 	// Specific addressing mode fetches.
 
@@ -167,8 +168,8 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 	// Sets up the next data access — its address and size/read flags.
 #define SetupDataAccess(addr, read_flag, select_flag)										\
 	access.address = access_announce.address = &addr;										\
-	access_announce.operation = Microcycle::NewAddress | Microcycle::IsData | read_flag;	\
-	access.operation = access_announce.operation | select_flag;
+	access_announce.operation = Microcycle::NewAddress | Microcycle::IsData | (read_flag);	\
+	access.operation = access_announce.operation | (select_flag);
 
 	// Performs the access established by SetupDataAccess into val.
 #define Access(val)										\
@@ -407,6 +408,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Access(operand_[next_operand_].low);	// nr
 		MoveToNextOperand(FetchOperand_bw);
 
+		// TODO: avoid use of temporary_address_ here and probably above.
 		BeginState(FetchAddressRegisterIndirect_l):
 			effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
 
@@ -414,6 +416,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Access(operand_[next_operand_].high);	// nR
 
 			temporary_address_ += 2;
+			effective_address_[next_operand_] += 2;
 			Access(operand_[next_operand_].low);	// nr
 		MoveToNextOperand(FetchOperand_l);
 
@@ -428,9 +431,24 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 				MoveToState(Decode);
 			}
 
-			// TODO: make a decision on how I'm going to deal with byte/word/longword.
-			assert(false);
-		break;
+			if(instruction_.operand_size() == InstructionSet::M68k::DataSize::LongWord) {
+				MoveToState(StoreOperand_l);
+			}
+
+			SetupDataAccess(
+				effective_address_[next_operand_],
+				0,
+				(instruction_.operand_size() == InstructionSet::M68k::DataSize::Byte) ? Microcycle::SelectByte : Microcycle::SelectWord);
+			Access(operand_[next_operand_].low);		// nw
+		MoveToState(Decode);
+
+		BeginState(StoreOperand_l):
+			SetupDataAccess(effective_address_[next_operand_], 0, Microcycle::SelectWord);
+			Access(operand_[next_operand_].low);		// nw
+
+			effective_address_[next_operand_] -= 2;
+			Access(operand_[next_operand_].high);		// nW
+		MoveToState(Decode);
 
 		//
 		// Various generic forms of perform.