From 28c7d27cac98671ea54de235e00aec21e9643432 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Fri, 6 Oct 2023 11:07:33 -0400 Subject: [PATCH] Establish some proportion of state, ready to execute _something_. --- .../Implementation/PerformImplementation.hpp | 3 +- InstructionSets/x86/Status.hpp | 6 ++++ OSBindings/Mac/Clock SignalTests/8088Tests.mm | 32 ++++++++++++++++--- 3 files changed, 36 insertions(+), 5 deletions(-) diff --git a/InstructionSets/x86/Implementation/PerformImplementation.hpp b/InstructionSets/x86/Implementation/PerformImplementation.hpp index 2ac3cfabe..eb879db40 100644 --- a/InstructionSets/x86/Implementation/PerformImplementation.hpp +++ b/InstructionSets/x86/Implementation/PerformImplementation.hpp @@ -287,7 +287,8 @@ template < // * return directly if there is definitely no possible write back to RAM; // * otherwise use the source() and destination() lambdas, and break in order to allow a writeback if necessary. switch(instruction.operation) { - default: assert(false); + default: return; + //assert(false); case Operation::AAA: Primitive::aaa(registers.axp(), status); return; case Operation::AAD: Primitive::aad(registers.axp(), instruction.operand(), status); return; diff --git a/InstructionSets/x86/Status.hpp b/InstructionSets/x86/Status.hpp index dbb9b4295..b1c4b2e1e 100644 --- a/InstructionSets/x86/Status.hpp +++ b/InstructionSets/x86/Status.hpp @@ -68,6 +68,12 @@ struct Status { // Convenience getters. template IntT carry_bit() { return carry ? 1 : 0; } + + void set(uint16_t value) { + carry = value & ConditionCode::Carry; + + // TODO: the rest. + } }; } diff --git a/OSBindings/Mac/Clock SignalTests/8088Tests.mm b/OSBindings/Mac/Clock SignalTests/8088Tests.mm index 8408895dd..7c5f53033 100644 --- a/OSBindings/Mac/Clock SignalTests/8088Tests.mm +++ b/OSBindings/Mac/Clock SignalTests/8088Tests.mm @@ -209,6 +209,7 @@ constexpr char TestSuiteHome[] = "/Users/tharte/Projects/ProcessorTests/8088/v1" uint16_t &di() { return di_; } uint16_t es_, cs_, ds_, ss_; + uint16_t ip_; }; struct Memory { std::vector memory; @@ -222,10 +223,10 @@ constexpr char TestSuiteHome[] = "/Users/tharte/Projects/ProcessorTests/8088/v1" uint32_t physical_address; using Source = InstructionSet::x86::Source; switch(segment) { - default: address = registers_.ds_; break; - case Source::ES: address = registers_.es_; break; - case Source::CS: address = registers_.cs_; break; - case Source::DS: address = registers_.ds_; break; + default: physical_address = registers_.ds_; break; + case Source::ES: physical_address = registers_.es_; break; + case Source::CS: physical_address = registers_.cs_; break; + case Source::DS: physical_address = registers_.ds_; break; } physical_address = ((physical_address << 4) + address) & 0xf'ffff; return *reinterpret_cast(&memory[physical_address]); @@ -242,6 +243,29 @@ constexpr char TestSuiteHome[] = "/Users/tharte/Projects/ProcessorTests/8088/v1" Memory memory(registers); IO io; + // Apply initial state. + NSDictionary *const initial = test[@"initial"]; + for(NSArray *ram in initial[@"ram"]) { + memory.memory[[ram[0] intValue]] = [ram[1] intValue]; + } + NSDictionary *const initial_registers = initial[@"regs"]; + registers.ax_.full = [initial_registers[@"ax"] intValue]; + registers.bx_.full = [initial_registers[@"bx"] intValue]; + registers.cx_.full = [initial_registers[@"cx"] intValue]; + registers.dx_.full = [initial_registers[@"dx"] intValue]; + + registers.bp_ = [initial_registers[@"bp"] intValue]; + registers.cs_ = [initial_registers[@"cs"] intValue]; + registers.di_ = [initial_registers[@"di"] intValue]; + registers.ds_ = [initial_registers[@"ds"] intValue]; + registers.es_ = [initial_registers[@"es"] intValue]; + registers.si_ = [initial_registers[@"si"] intValue]; + registers.sp_ = [initial_registers[@"sp"] intValue]; + registers.ss_ = [initial_registers[@"ss"] intValue]; + registers.ip_ = [initial_registers[@"ip"] intValue]; + + status.set([initial_registers[@"flags"] intValue]); + InstructionSet::x86::perform( decoded.second, status,