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Makes first attempt at giving the Z80 something to do.
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@ -23,7 +23,7 @@ class ConcreteMachine:
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public MachineTypes::ScanProducer,
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public MachineTypes::ScanProducer,
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public MachineTypes::TimedMachine {
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public MachineTypes::TimedMachine {
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public:
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public:
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ConcreteMachine(const Analyser::Static::Enterprise::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
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ConcreteMachine([[maybe_unused]] const Analyser::Static::Enterprise::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
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z80_(*this) {
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z80_(*this) {
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// Request a clock of 4Mhz; this'll be mapped upwards for Nick and Dave elsewhere.
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// Request a clock of 4Mhz; this'll be mapped upwards for Nick and Dave elsewhere.
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set_clock_rate(4'000'000);
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set_clock_rate(4'000'000);
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@ -34,8 +34,45 @@ class ConcreteMachine:
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throw ROMMachine::Error::MissingROMs;
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throw ROMMachine::Error::MissingROMs;
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}
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}
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(void)target;
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// Take a reasonable guess at the initial memory configuration.
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(void)rom_fetcher;
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page<0>(0x00);
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page<1>(0x01);
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page<2>(0xfe);
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page<3>(0xff);
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}
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// MARK: - Z80::BusHandler.
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forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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using PartialMachineCycle = CPU::Z80::PartialMachineCycle;
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const uint16_t address = cycle.address ? *cycle.address : 0x0000;
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// TODO: possibly apply an access penalty.
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switch(cycle.operation) {
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default: break;
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case CPU::Z80::PartialMachineCycle::Input:
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case CPU::Z80::PartialMachineCycle::Output:
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assert(false);
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break;
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case CPU::Z80::PartialMachineCycle::Read:
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case CPU::Z80::PartialMachineCycle::ReadOpcode:
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if(read_pointers_[address >> 14]) {
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*cycle.value = read_pointers_[address >> 14][address];
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} else {
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*cycle.value = 0xff;
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}
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break;
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case CPU::Z80::PartialMachineCycle::Write:
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if(write_pointers_[address >> 14]) {
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write_pointers_[address >> 14][address] = *cycle.value;
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}
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break;
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}
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return HalfCycles(0);
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}
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}
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private:
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private:
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@ -43,11 +80,32 @@ class ConcreteMachine:
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std::array<uint8_t, 32 * 1024> exos_;
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std::array<uint8_t, 32 * 1024> exos_;
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std::array<uint8_t, 256 * 1024> ram_;
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std::array<uint8_t, 256 * 1024> ram_;
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const uint8_t min_ram_slot_ = 0xff - 3;
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// MARK: - Z80::BusHandler.
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const uint8_t *read_pointers_[4];
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forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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uint8_t *write_pointers_[4];
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(void)cycle;
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uint8_t pages_[4];
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return HalfCycles(0);
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template <size_t slot> void page(uint8_t offset) {
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pages_[slot] = offset;
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if(offset < 2) {
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page<slot>(&exos_[offset * 0x4000], nullptr);
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return;
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}
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if(offset >= min_ram_slot_) {
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const size_t address = (offset - min_ram_slot_) * 0x4000;
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page<slot>(&ram_[address], &ram_[address]);
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return;
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}
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page<slot>(nullptr, nullptr);
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}
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template <size_t slot> void page(const uint8_t *read, uint8_t *write) {
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read_pointers_[slot] = read ? read - (slot * 0x4000) : nullptr;
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write_pointers_[slot] = write ? write - (slot * 0x4000) : nullptr;
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}
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}
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// MARK: - ScanProducer
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// MARK: - ScanProducer
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@ -61,7 +119,7 @@ class ConcreteMachine:
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// MARK: - TimedMachine
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// MARK: - TimedMachine
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void run_for(const Cycles cycles) override {
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void run_for(const Cycles cycles) override {
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(void)cycles;
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z80_.run_for(cycles);
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}
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}
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};
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};
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