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Merge pull request #723 from TomHarte/LSLTiming
Introduces a timing test for LSL. Which already passes.
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commit
2c742a051e
@ -261,6 +261,32 @@ class CPU::MC68000::ProcessorStorageTests {
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XCTAssertEqual(stack_frame[6], 0x1004);
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XCTAssertEqual(stack_frame[6], 0x1004);
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}
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}
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- (void)testShiftDuration {
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//
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_machine->set_program({
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0x7004, // MOVE.l #$4, D0
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0x7207, // MOVE.l #$7, D1
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0x7401, // MOVE.l #$1, D2
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0xe16e, // lsl d0, d6
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0xe36e, // lsl d1, d6
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0xe56e, // lsl d2, d6
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});
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_machine->run_for_instructions(3);
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_machine->reset_cycle_count();
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_machine->run_for_instructions(1);
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XCTAssertEqual(_machine->get_cycle_count(), 6 + 8);
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_machine->reset_cycle_count();
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_machine->run_for_instructions(1);
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XCTAssertEqual(_machine->get_cycle_count(), 6 + 14);
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_machine->reset_cycle_count();
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_machine->run_for_instructions(1);
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XCTAssertEqual(_machine->get_cycle_count(), 6 + 2);
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}
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- (void)testOpcodeCoverage {
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- (void)testOpcodeCoverage {
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// Perform an audit of implemented instructions.
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// Perform an audit of implemented instructions.
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CPU::MC68000::ProcessorStorageTests storage_tests(
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CPU::MC68000::ProcessorStorageTests storage_tests(
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@ -130,6 +130,10 @@ class RAM68000: public CPU::MC68000::BusHandler {
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return int(duration_.as_integral()) >> 1;
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return int(duration_.as_integral()) >> 1;
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}
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}
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void reset_cycle_count() {
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duration_ = HalfCycles(0);
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}
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private:
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private:
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CPU::MC68000::Processor<RAM68000, true, true> m68000_;
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CPU::MC68000::Processor<RAM68000, true, true> m68000_;
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std::array<uint16_t, 256*1024> ram_{};
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std::array<uint16_t, 256*1024> ram_{};
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