6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-19 08:31:11 +00:00
Code Issues Projects Releases Wiki Activity

Imports CMPM tests and fixes CMPM.bw source/destination order.

Browse Source
This commit is contained in:
Thomas Harte 2019-06-25 21:46:01 -04:00
parent d2cb595b83
commit 2c813a2692
2 changed files with 74 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

65
OSBindings/Mac/Clock SignalTests/68000Tests.mm
View File

@ -1494,6 +1494,71 @@ class CPU::MC68000::ProcessorStorageTests {
XCTAssertEqual(44, _machine->get_cycle_count()); XCTAssertEqual(44, _machine->get_cycle_count());
} }
// MARK: CMPM
- (void)testCMPMl {
_machine->set_program({
0xb389 // CMPM.L (A1)+, (A1)+
});
auto state = _machine->get_processor_state();
state.address[1] = 0x3000;
state.status |= Flag::ConditionCodes;
*_machine->ram_at(0x3000) = 0x7000;
*_machine->ram_at(0x3002) = 0x1ff1;
*_machine->ram_at(0x3004) = 0x1000;
*_machine->ram_at(0x3006) = 0x0000;
_machine->set_processor_state(state);
_machine->run_for_instructions(1);
state = _machine->get_processor_state();
XCTAssertEqual(state.address[1], 0x3008);
XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend | Flag::Carry);
XCTAssertEqual(20, _machine->get_cycle_count());
}
- (void)testCMPMw {
_machine->set_program({
0xb549 // CMPM.w (A1)+, (A2)+
});
auto state = _machine->get_processor_state();
state.address[1] = 0x3000;
state.address[2] = 0x3002;
state.status |= Flag::ConditionCodes;
*_machine->ram_at(0x3000) = 0;
*_machine->ram_at(0x3002) = 0;
_machine->set_processor_state(state);
_machine->run_for_instructions(1);
state = _machine->get_processor_state();
XCTAssertEqual(state.address[1], 0x3002);
XCTAssertEqual(state.address[2], 0x3004);
XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero | Flag::Extend);
XCTAssertEqual(12, _machine->get_cycle_count());
}
- (void)testCMPMb {
_machine->set_program({
0xb509 // CMPM.b (A1)+, (A2)+
});
auto state = _machine->get_processor_state();
state.address[1] = 0x3000;
state.address[2] = 0x3001;
state.status |= Flag::ConditionCodes;
*_machine->ram_at(0x3000) = 0x807f;
_machine->set_processor_state(state);
_machine->run_for_instructions(1);
state = _machine->get_processor_state();
XCTAssertEqual(state.address[1], 0x3001);
XCTAssertEqual(state.address[2], 0x3002);
XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend | Flag::Carry | Flag::Overflow);
XCTAssertEqual(12, _machine->get_cycle_count());
}
// MARK: DBcc // MARK: DBcc
- (void)performDBccTestOpcode:(uint16_t)opcode status:(uint16_t)status d2Outcome:(uint32_t)d2Output { - (void)performDBccTestOpcode:(uint16_t)opcode status:(uint16_t)status d2Outcome:(uint32_t)d2Output {

18
Processors/68000/Implementation/68000Storage.cpp
View File

@ -2279,8 +2279,8 @@ struct ProcessorStorageConstructor {
} break; } break;
case Decoder::CMPM: { case Decoder::CMPM: {
program.set_source(storage_, 1, ea_register); program.set_source(storage_, PostInc, ea_register);
program.set_destination(storage_, 1, data_register); program.set_destination(storage_, PostInc, data_register);
const bool is_byte_operation = operation == Operation::CMPb; const bool is_byte_operation = operation == Operation::CMPb;
@ -2288,15 +2288,15 @@ struct ProcessorStorageConstructor {
default: continue; default: continue;
case Operation::CMPb: // CMPM.b, (An)+, (An)+ case Operation::CMPb: // CMPM.b, (An)+, (An)+
case Operation::CMPw: { // CMPM.w, (An)+, (An)+ case Operation::CMPw: // CMPM.w, (An)+, (An)+
op(Action::None, seq("nr", { a(data_register) }, !is_byte_operation)); op(Action::None, seq("nr", { a(ea_register) }, !is_byte_operation));
op( inc(data_register) | MicroOp::SourceMask, op( inc(ea_register) | MicroOp::SourceMask,
seq("nrd np", { a(ea_register) }, !is_byte_operation)); seq("nrd np", { a(data_register) }, !is_byte_operation));
op(inc(ea_register) | MicroOp::DestinationMask); op(inc(data_register) | MicroOp::DestinationMask);
op(Action::PerformOperation); op(Action::PerformOperation);
} break; break;
case Operation::CMPl: case Operation::CMPl: // CMPM.l, (An)+, (An)+
op( int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask, op( int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask,
seq("nR+ nr", {ea(0), ea(0)})); seq("nR+ nr", {ea(0), ea(0)}));
op(int(Action::Increment4) | MicroOp::SourceMask); op(int(Action::Increment4) | MicroOp::SourceMask);