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Implement JSR.
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@@ -579,7 +579,23 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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);
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goto jammed;
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// MARK: - Flow control (other than BRK).
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case access_program(JSR):
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++registers.pc.full;
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access(BusOperation::Read, Stack(registers.s), throwaway);
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access(BusOperation::Write, Stack(registers.dec_s()), registers.pc.halves.high);
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access(BusOperation::Write, Stack(registers.dec_s()), registers.pc.halves.low);
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check_interrupt();
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access(BusOperation::Read, Literal(registers.pc.full), registers.pc.halves.high);
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registers.pc.halves.low = Storage::operand_;
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goto fetch_decode;
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// MARK: - NMI/IRQ/Reset, and BRK.
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case access_program(BRK):
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++registers.pc.full;
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access(BusOperation::Write, Stack(registers.dec_s()), registers.pc.halves.high);
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