6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2025-08-09 05:25:01 +00:00
Code Issues Projects Releases Wiki Activity

Added diagnosis props.

Browse Source
This commit is contained in:
Thomas Harte
2017-05-31 06:54:25 -04:00
parent 5119997122
commit 2f7f11e2e5
2 changed files with 7 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
OSBindings/Mac/Clock SignalTests/FUSETests.swift
View File

@@ -167,9 +167,10 @@ class FUSETests: XCTestCase {
let name = itemDictionary["name"] as! String let name = itemDictionary["name"] as! String
if name != "02" { // if name != "02" {
continue; // continue;
} // }
print("\(name)")
let initialState = RegisterState(dictionary: itemDictionary["state"] as! [String: Any]) let initialState = RegisterState(dictionary: itemDictionary["state"] as! [String: Any])
let targetState = RegisterState(dictionary: outputDictionary["state"] as! [String: Any]) let targetState = RegisterState(dictionary: outputDictionary["state"] as! [String: Any])

3
Processors/Z80/Z80AllRAM.cpp
View File

@@ -20,11 +20,14 @@ class ConcreteAllRAMProcessor: public AllRAMProcessor, public Processor<Concrete
uint16_t address = cycle.address ? *cycle.address : 0x0000; uint16_t address = cycle.address ? *cycle.address : 0x0000;
switch(cycle.operation) { switch(cycle.operation) {
case BusOperation::ReadOpcode: case BusOperation::ReadOpcode:
printf("! ");
check_address_for_trap(address); check_address_for_trap(address);
case BusOperation::Read: case BusOperation::Read:
printf("r %04x [%02x] AF:%04x BC:%04x DE:%04x HL:%04x SP:%04x\n", address, memory_[address], get_value_of_register(CPU::Z80::Register::AF), get_value_of_register(CPU::Z80::Register::BC), get_value_of_register(CPU::Z80::Register::DE), get_value_of_register(CPU::Z80::Register::HL), get_value_of_register(CPU::Z80::Register::StackPointer));
*cycle.value = memory_[address]; *cycle.value = memory_[address];
break; break;
case BusOperation::Write: case BusOperation::Write:
printf("w %04x\n", address);
memory_[address] = *cycle.value; memory_[address] = *cycle.value;
break; break;