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Ups the 65816 test machine to a full 16mb RAM.

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This commit is contained in:
Thomas Harte 2020-10-11 21:18:01 -04:00
parent 82797fd395
commit 3039a445f0
4 changed files with 13 additions and 12 deletions
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7
Processors/6502/AllRAM/6502AllRAM.cpp
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@ -21,12 +21,13 @@ using Type = CPU::MOS6502Esque::Type;
template <Type type> class ConcreteAllRAMProcessor: public AllRAMProcessor, public BusHandler { template <Type type> class ConcreteAllRAMProcessor: public AllRAMProcessor, public BusHandler {
public: public:
ConcreteAllRAMProcessor() : ConcreteAllRAMProcessor(size_t memory_size) :
AllRAMProcessor(memory_size),
mos6502_(*this) { mos6502_(*this) {
mos6502_.set_power_on(false); mos6502_.set_power_on(false);
} }
inline Cycles perform_bus_operation(BusOperation operation, uint16_t address, uint8_t *value) { inline Cycles perform_bus_operation(BusOperation operation, uint32_t address, uint8_t *value) {
timestamp_ += Cycles(1); timestamp_ += Cycles(1);
if(operation == BusOperation::ReadOpcode) { if(operation == BusOperation::ReadOpcode) {
@ -91,7 +92,7 @@ template <Type type> class ConcreteAllRAMProcessor: public AllRAMProcessor, publ
} }
AllRAMProcessor *AllRAMProcessor::Processor(Type type) { AllRAMProcessor *AllRAMProcessor::Processor(Type type) {
#define Bind(p) case p: return new ConcreteAllRAMProcessor<p>(); #define Bind(p) case p: return new ConcreteAllRAMProcessor<p>(type == Type::TWDC65816 ? 16*1024*1024 : 64*1024);
switch(type) { switch(type) {
default: default:
Bind(Type::T6502) Bind(Type::T6502)

2
Processors/6502/AllRAM/6502AllRAM.hpp
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@ -29,7 +29,7 @@ class AllRAMProcessor:
virtual void set_value_of_register(Register r, uint16_t value) = 0; virtual void set_value_of_register(Register r, uint16_t value) = 0;
protected: protected:
AllRAMProcessor() : ::CPU::AllRAMProcessor(65536) {} AllRAMProcessor(size_t memory_size) : ::CPU::AllRAMProcessor(memory_size) {}
}; };
} }

12
Processors/AllRAMProcessor.cpp
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@ -15,14 +15,14 @@ AllRAMProcessor::AllRAMProcessor(std::size_t memory_size) :
traps_(memory_size, false), traps_(memory_size, false),
timestamp_(0) {} timestamp_(0) {}
void AllRAMProcessor::set_data_at_address(uint16_t startAddress, std::size_t length, const uint8_t *data) { void AllRAMProcessor::set_data_at_address(size_t start_address, std::size_t length, const uint8_t *data) {
std::size_t endAddress = std::min(startAddress + length, size_t(65536)); const size_t end_address = std::min(start_address + length, memory_.size());
std::memcpy(&memory_[startAddress], data, endAddress - startAddress); memcpy(&memory_[start_address], data, end_address - start_address);
} }
void AllRAMProcessor::get_data_at_address(uint16_t startAddress, std::size_t length, uint8_t *data) { void AllRAMProcessor::get_data_at_address(size_t start_address, std::size_t length, uint8_t *data) {
std::size_t endAddress = std::min(startAddress + length, size_t(65536)); const size_t end_address = std::min(start_address + length, memory_.size());
std::memcpy(data, &memory_[startAddress], endAddress - startAddress); memcpy(data, &memory_[start_address], end_address - start_address);
} }
HalfCycles AllRAMProcessor::get_timestamp() { HalfCycles AllRAMProcessor::get_timestamp() {

4
Processors/AllRAMProcessor.hpp
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@ -21,8 +21,8 @@ class AllRAMProcessor {
public: public:
AllRAMProcessor(std::size_t memory_size); AllRAMProcessor(std::size_t memory_size);
HalfCycles get_timestamp(); HalfCycles get_timestamp();
void set_data_at_address(uint16_t startAddress, std::size_t length, const uint8_t *data); void set_data_at_address(size_t startAddress, size_t length, const uint8_t *data);
void get_data_at_address(uint16_t startAddress, std::size_t length, uint8_t *data); void get_data_at_address(size_t startAddress, size_t length, uint8_t *data);
class TrapHandler { class TrapHandler {
public: public: