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Merge pull request #704 from TomHarte/RTR

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Corrects implementation of RTR
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Thomas Harte 2019-12-25 20:47:21 -05:00 committed by GitHub
commit 314973a5ef
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4 changed files with 1036 additions and 6 deletions
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1025
OSBindings/Mac/Clock SignalTests/68000 Comparative Tests/rtr.json Normal file
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3
OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm
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@ -27,7 +27,7 @@
- (void)setUp {
// To limit tests run to a subset of files and/or of tests, uncomment and fill in below.
// _fileSet = [NSSet setWithArray:@[@"eor.json"]];
// _fileSet = [NSSet setWithArray:@[@"rtr.json"]];
// _testSet = [NSSet setWithArray:@[@"EOR b0c0", @"EOR b0c2", @"EOR b0c3", @"EOR b0c5", @"EOR b0c6", @"EOR b0c7", @"OR b0c7"]];
}
@ -172,6 +172,7 @@
XCTAssertEqual(state.supervisor_stack_pointer, [finalState[@"a7"] integerValue], @"%@: A7 inconsistent", name);
XCTAssertEqual(state.user_stack_pointer, [finalState[@"usp"] integerValue], @"%@: USP inconsistent", name);
XCTAssertEqual(state.status, [finalState[@"sr"] integerValue], @"%@: Status inconsistent", name);
XCTAssertEqual(state.program_counter - 4, [finalState[@"pc"] integerValue], @"%@: Program counter inconsistent", name);
// Test final memory state.
NSArray<NSNumber *> *const finalMemory = test[@"final memory"];

8
Processors/68000/Implementation/68000Implementation.hpp
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@ -1854,11 +1854,11 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
RTE and RTR share an implementation.
*/
case Operation::RTE_RTR:
// If this is RTR, patch out the is_supervisor bit.
// If this is RTR, patch out the supervisor half of the status register.
if(decoded_instruction_.full == 0x4e77) {
source_bus_data_[0].full =
(source_bus_data_[0].full & uint32_t(~(1 << 13))) |
uint32_t(is_supervisor_ << 13);
const auto current_status = get_status();
source_bus_data_[0].halves.low.halves.high =
uint8_t(current_status >> 8);
}
set_status(source_bus_data_[0].full);
break;

6
Processors/68000/Implementation/68000Storage.cpp
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@ -1013,7 +1013,11 @@ struct ProcessorStorageConstructor {
case Decoder::RTE_RTR: {
program.set_requires_supervisor(instruction == 0x4e73);
// TODO: something explicit to ensure the nR nr nr is exclusively linked.
// The targets of the nR nr nr below are reset to the program counter elsewhere;
// look for the comment "relink the RTE and RTR bus steps". It is currently not
// explicitly tested that these bus steps are not shared with a non-RTE/RTR operation,
// just assumed because the repetition of nr is fairly silly. A more explicit soution
// might be preferable in the future.
op(Action::PrepareRTE_RTR, seq("nR nr nr", { &storage_.precomputed_addresses_[0], &storage_.precomputed_addresses_[1], &storage_.precomputed_addresses_[2] } ));
op(Action::PerformOperation, seq("np np"));
op();