mirror of
https://github.com/TomHarte/CLK.git
synced 2024-11-19 08:31:11 +00:00
Muddles drunkenly towards decoding ModRM.
This commit is contained in:
Thomas Harte
parent
9c5dc0ed29
commit
32c942d154
@ -8,26 +8,27 @@
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#include "x86.hpp"
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#include <cassert>
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using namespace CPU::Decoder::x86;
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Instruction Decoder::decode(uint8_t *source, size_t length) {
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uint8_t *const limit = source + length;
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#define MapPartial(value, op, sz, fmt, phs) \
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case value: \
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operation_ = Operation::op; \
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operand_size_ = Size::sz; \
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format_ = Format::fmt; \
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phase_ = Phase::phs; \
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#define MapPartial(value, op, lrg, fmt, phs) \
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case value: \
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operation_ = Operation::op; \
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large_operand_ = lrg; \
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format_ = Format::fmt; \
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phase_ = Phase::phs; \
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break
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#define MapComplete(value, op, sz, src, dest) \
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case value: \
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operation_ = Operation::op; \
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operand_size_ = Size::sz; \
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source_ = Source::src; \
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destination_ = Source::dest; \
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phase_ = Phase::ReadyToPost; \
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#define MapComplete(value, op, src, dest) \
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case value: \
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operation_ = Operation::op; \
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source_ = Source::src; \
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destination_ = Source::dest; \
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phase_ = Phase::ReadyToPost; \
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break
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while(phase_ == Phase::Instruction && source != limit) {
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@ -36,56 +37,56 @@ Instruction Decoder::decode(uint8_t *source, size_t length) {
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instr_ = *source;
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switch(instr_) {
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#define PartialBlock(start, operation) \
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MapPartial(start + 0x00, operation, Byte, MemReg_Reg, ModRM); \
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MapPartial(start + 0x01, operation, Word, MemReg_Reg, ModRM); \
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MapPartial(start + 0x02, operation, Byte, Reg_MemReg, ModRM); \
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MapPartial(start + 0x03, operation, Word, Reg_MemReg, ModRM); \
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MapPartial(start + 0x04, operation, Byte, Ac_Data, AwaitingOperands); \
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MapPartial(start + 0x05, operation, Word, Ac_Data, AwaitingOperands);
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MapPartial(start + 0x00, operation, false, MemReg_Reg, ModRM); \
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MapPartial(start + 0x01, operation, true, MemReg_Reg, ModRM); \
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MapPartial(start + 0x02, operation, false, Reg_MemReg, ModRM); \
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MapPartial(start + 0x03, operation, true, Reg_MemReg, ModRM); \
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MapPartial(start + 0x04, operation, false, Ac_Data, AwaitingOperands); \
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MapPartial(start + 0x05, operation, true, Ac_Data, AwaitingOperands);
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PartialBlock(0x00, ADD);
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MapComplete(0x06, PUSH, Word, ES, None);
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MapComplete(0x07, POP, Word, ES, None);
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MapComplete(0x06, PUSH, ES, None);
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MapComplete(0x07, POP, ES, None);
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PartialBlock(0x08, OR);
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MapComplete(0x0e, PUSH, Word, CS, None);
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MapComplete(0x0e, PUSH, CS, None);
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/* 0x0f: not used. */
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PartialBlock(0x10, ADC);
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MapComplete(0x16, PUSH, Word, SS, None);
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MapComplete(0x17, POP, Word, SS, None);
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MapComplete(0x16, PUSH, SS, None);
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MapComplete(0x17, POP, SS, None);
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PartialBlock(0x18, SBB);
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MapComplete(0x1e, PUSH, Word, DS, None);
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MapComplete(0x1f, POP, Word, DS, None);
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MapComplete(0x1e, PUSH, DS, None);
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MapComplete(0x1f, POP, DS, None);
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PartialBlock(0x20, AND);
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case 0x26: segment_override_ = Source::ES; break;
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MapComplete(0x27, DAA, Implied, None, None);
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MapComplete(0x27, DAA, None, None);
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PartialBlock(0x28, SUB);
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case 0x2e: segment_override_ = Source::CS; break;
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MapComplete(0x2f, DAS, Implied, None, None);
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MapComplete(0x2f, DAS, None, None);
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PartialBlock(0x30, XOR);
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case 0x36: segment_override_ = Source::SS; break;
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MapComplete(0x37, AAA, Implied, None, None);
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MapComplete(0x37, AAA, None, None);
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PartialBlock(0x38, CMP);
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case 0x3e: segment_override_ = Source::DS; break;
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MapComplete(0x3f, AAS, Implied, None, None);
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MapComplete(0x3f, AAS, None, None);
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#undef PartialBlock
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#define RegisterBlock(start, operation) \
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MapComplete(start + 0x00, operation, Word, AX, AX); \
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MapComplete(start + 0x01, operation, Word, CX, CX); \
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MapComplete(start + 0x02, operation, Word, DX, DX); \
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MapComplete(start + 0x03, operation, Word, BX, BX); \
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MapComplete(start + 0x04, operation, Word, SP, SP); \
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MapComplete(start + 0x05, operation, Word, BP, BP); \
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MapComplete(start + 0x06, operation, Word, SI, SI); \
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MapComplete(start + 0x07, operation, Word, DI, DI); \
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MapComplete(start + 0x00, operation, AX, AX); \
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MapComplete(start + 0x01, operation, CX, CX); \
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MapComplete(start + 0x02, operation, DX, DX); \
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MapComplete(start + 0x03, operation, BX, BX); \
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MapComplete(start + 0x04, operation, SP, SP); \
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MapComplete(start + 0x05, operation, BP, BP); \
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MapComplete(start + 0x06, operation, SI, SI); \
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MapComplete(start + 0x07, operation, DI, DI); \
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RegisterBlock(0x40, INC);
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RegisterBlock(0x48, DEC);
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@ -96,59 +97,68 @@ Instruction Decoder::decode(uint8_t *source, size_t length) {
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/* 0x60–0x6f: not used. */
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MapPartial(0x70, JO, Byte, Disp, AwaitingOperands);
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MapPartial(0x71, JNO, Byte, Disp, AwaitingOperands);
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MapPartial(0x72, JB, Byte, Disp, AwaitingOperands);
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MapPartial(0x73, JNB, Byte, Disp, AwaitingOperands);
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MapPartial(0x74, JE, Byte, Disp, AwaitingOperands);
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MapPartial(0x75, JNE, Byte, Disp, AwaitingOperands);
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MapPartial(0x76, JBE, Byte, Disp, AwaitingOperands);
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MapPartial(0x77, JNBE, Byte, Disp, AwaitingOperands);
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MapPartial(0x78, JS, Byte, Disp, AwaitingOperands);
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MapPartial(0x79, JNS, Byte, Disp, AwaitingOperands);
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MapPartial(0x7a, JP, Byte, Disp, AwaitingOperands);
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MapPartial(0x7b, JNP, Byte, Disp, AwaitingOperands);
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MapPartial(0x7c, JL, Byte, Disp, AwaitingOperands);
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MapPartial(0x7d, JNL, Byte, Disp, AwaitingOperands);
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MapPartial(0x7e, JLE, Byte, Disp, AwaitingOperands);
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MapPartial(0x7f, JNLE, Byte, Disp, AwaitingOperands);
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#define MapJump(value, operation) MapPartial(value, operation, false, Disp, AwaitingOperands);
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MapJump(0x70, JO);
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MapJump(0x71, JNO);
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MapJump(0x72, JB);
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MapJump(0x73, JNB);
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MapJump(0x74, JE);
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MapJump(0x75, JNE);
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MapJump(0x76, JBE);
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MapJump(0x77, JNBE);
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MapJump(0x78, JS);
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MapJump(0x79, JNS);
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MapJump(0x7a, JP);
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MapJump(0x7b, JNP);
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MapJump(0x7c, JL);
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MapJump(0x7d, JNL);
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MapJump(0x7e, JLE);
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MapJump(0x7f, JNLE);
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#undef MapJump
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// TODO:
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//
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// 0x80, 0x81, 0x82, 0x83, which all require more
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// input, from the ModRM byte.
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MapPartial(0x84, TEST, Byte, MemReg_Reg, ModRM);
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MapPartial(0x85, TEST, Word, MemReg_Reg, ModRM);
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MapPartial(0x86, XCHG, Byte, Reg_MemReg, ModRM);
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MapPartial(0x87, XCHG, Word, Reg_MemReg, ModRM);
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MapPartial(0x88, MOV, Byte, MemReg_Reg, ModRM);
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MapPartial(0x89, MOV, Word, MemReg_Reg, ModRM);
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MapPartial(0x8a, MOV, Byte, Reg_MemReg, ModRM);
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MapPartial(0x8b, MOV, Word, Reg_MemReg, ModRM);
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MapPartial(0x84, TEST, false, MemReg_Reg, ModRM);
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MapPartial(0x85, TEST, true, MemReg_Reg, ModRM);
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MapPartial(0x86, XCHG, false, Reg_MemReg, ModRM);
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MapPartial(0x87, XCHG, true, Reg_MemReg, ModRM);
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MapPartial(0x88, MOV, false, MemReg_Reg, ModRM);
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MapPartial(0x89, MOV, true, MemReg_Reg, ModRM);
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MapPartial(0x8a, MOV, false, Reg_MemReg, ModRM);
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MapPartial(0x8b, MOV, true, Reg_MemReg, ModRM);
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/* 0x8c: not used. */
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MapPartial(0x8d, LEA, Word, Reg_Addr, ModRM);
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MapPartial(0x8e, MOV, Word, SegReg_MemReg, ModRM);
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MapPartial(0x8d, LEA, true, Reg_Addr, ModRM);
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MapPartial(0x8e, MOV, true, SegReg_MemReg, ModRM);
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// TODO: 0x8f, which requires further selection from the ModRM byte.
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MapComplete(0x90, NOP, Implied, None, None); // Or XCHG AX, AX?
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MapComplete(0x91, XCHG, Word, AX, CX);
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MapComplete(0x92, XCHG, Word, AX, DX);
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MapComplete(0x93, XCHG, Word, AX, BX);
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MapComplete(0x94, XCHG, Word, AX, SP);
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MapComplete(0x95, XCHG, Word, AX, BP);
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MapComplete(0x96, XCHG, Word, AX, SI);
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MapComplete(0x97, XCHG, Word, AX, DI);
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MapComplete(0x90, NOP, None, None); // Or XCHG AX, AX?
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MapComplete(0x91, XCHG, AX, CX);
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MapComplete(0x92, XCHG, AX, DX);
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MapComplete(0x93, XCHG, AX, BX);
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MapComplete(0x94, XCHG, AX, SP);
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MapComplete(0x95, XCHG, AX, BP);
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MapComplete(0x96, XCHG, AX, SI);
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MapComplete(0x97, XCHG, AX, DI);
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MapComplete(0x98, CBW, Implied, None, None);
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MapComplete(0x99, CWD, Implied, None, None);
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MapPartial(0x9a, CALL, Word, Disp, AwaitingOperands);
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MapComplete(0x9b, WAIT, Implied, None, None);
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MapComplete(0x9c, PUSHF, Implied, None, None);
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MapComplete(0x9d, POPF, Implied, None, None);
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MapComplete(0x9e, SAHF, Implied, None, None);
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MapComplete(0x9f, LAHF, Implied, None, None);
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MapComplete(0x98, CBW, None, None);
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MapComplete(0x99, CWD, None, None);
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MapPartial(0x9a, CALL, true, Addr, AwaitingOperands);
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MapComplete(0x9b, WAIT, None, None);
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MapComplete(0x9c, PUSHF, None, None);
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MapComplete(0x9d, POPF, None, None);
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MapComplete(0x9e, SAHF, None, None);
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MapComplete(0x9f, LAHF, None, None);
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MapPartial(0xa0, MOV, false, Reg_Addr, AwaitingOperands);
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// Other prefix bytes.
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case 0xf0: lock_ = true; break;
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case 0xf2: repetition_ = Repetition::RepNE; break;
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case 0xf3: repetition_ = Repetition::RepE; break;
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}
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++source;
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++consumed_;
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@ -156,6 +166,74 @@ Instruction Decoder::decode(uint8_t *source, size_t length) {
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#undef MapInstr
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if(phase_ == Phase::ModRM && source != limit) {
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const uint8_t mod = *source >> 6; // i.e. mode.
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const uint8_t reg = (*source >> 3) & 7; // i.e. register.
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const uint8_t rm = *source & 7; // i.e. register/memory.
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switch(format_) {
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case Format::Reg_MemReg:
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case Format::MemReg_Reg: {
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Source memreg;
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constexpr Source reg_table[2][8] = {
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{
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Source::AL, Source::CL, Source::DL, Source::BL,
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Source::AH, Source::CH, Source::DH, Source::BH,
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}, {
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Source::AX, Source::CX, Source::DX, Source::BX,
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Source::SP, Source::BP, Source::SI, Source::DI,
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}
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};
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switch(mod) {
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case 0: {
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add_offset_ = false;
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constexpr Source rm_table[8] = {
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Source::IndBXPlusSI, Source::IndBXPlusDI,
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Source::IndBPPlusSI, Source::IndBPPlusDI,
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Source::IndSI, Source::IndDI,
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Source::DirectAddress, Source::IndBX,
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};
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memreg = rm_table[rm];
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} break;
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default: {
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add_offset_ = true;
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large_offset_ = (mod == 2);
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constexpr Source rm_table[8] = {
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Source::IndBXPlusSI, Source::IndBXPlusDI,
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Source::IndBPPlusSI, Source::IndBPPlusDI,
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Source::IndSI, Source::IndDI,
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Source::IndBP, Source::IndBX,
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};
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memreg = rm_table[rm];
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} break;
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// Other operand is just a register.
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case 3: memreg = reg_table[large_operand_][rm]; break;
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}
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if(format_ == Format::Reg_MemReg) {
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destination_ = reg_table[large_operand_][reg];
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source_ = memreg;
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} else {
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source_ = reg_table[large_operand_][reg];
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destination_ = memreg;
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}
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phase_ = (add_offset_ || memreg == Source::DirectAddress) ? Phase::AwaitingOperands : Phase::ReadyToPost;
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} break;
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default: assert(false);
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}
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++source;
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++consumed_;
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}
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if(phase_ == Phase::AwaitingOperands && source != limit) {
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// TODO: calculate number of expected operands.
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}
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if(phase_ == Phase::ReadyToPost) {
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// TODO: construct actual Instruction.
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@ -46,6 +46,7 @@ enum class Size: uint8_t {
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Implied = 0,
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Byte = 1,
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Word = 2,
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DWord = 4,
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};
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enum class Source: uint8_t {
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@ -60,7 +61,17 @@ enum class Source: uint8_t {
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SI, DI,
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BP, SP,
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Memory, Immediate
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IndBXPlusSI,
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IndBXPlusDI,
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IndBPPlusSI,
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IndBPPlusDI,
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IndSI,
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IndDI,
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DirectAddress,
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IndBP,
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IndBX,
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Immediate
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};
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class Instruction {
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@ -111,16 +122,28 @@ struct Decoder {
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MemReg_Data,
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SegReg_MemReg,
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Reg_Addr,
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Disp
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Addr_Reg,
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Disp,
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Addr
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} format_ = Format::MemReg_Reg;
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// TODO: figure out which Formats can be folded together,
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// and which are improperly elided.
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enum class Repetition: uint8_t {
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None, RepE, RepNE
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} repetition_ = Repetition::None;
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int consumed_ = 0;
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Operation operation_ = Operation::Invalid;
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Size operand_size_ = Size::Implied;
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bool large_operand_ = false;
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Source source_ = Source::None;
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Source destination_ = Source::None;
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Source segment_override_ = Source::None;
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uint8_t instr_ = 0x00;
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bool lock_ = false;
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bool add_offset_ = false;
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bool large_offset_ = false;
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};
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}
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