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Test lwzx.

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This commit is contained in:
Thomas Harte 2022-03-25 20:23:21 -04:00
parent 73ae7ad82f
commit 33c31eb798
2 changed files with 19 additions and 42 deletions
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9
InstructionSets/PowerPC/Instruction.hpp
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@ -151,7 +151,14 @@ enum class Operation: uint8_t {
fnabsx, fnegx, fnmaddx, fnmaddsx, fnmsubx, fnmsubsx, frspx, fsubx, fsubsx,
icbi, isync, lbz, lbzu, lbzux, lbzx, lfd, lfdu, lfdux, lfdx, lfs, lfsu,
lfsux, lfsx, lha, lhau, lhaux, lhax, lhbrx, lhz, lhzu, lhzux, lhzx, lmw,
lswi, lswx, lwarx, lwbrx, lwz, lwzu, lwzux, lwzx, mcrf, mcrfs, mcrxr,
lswi, lswx, lwarx, lwbrx, lwz, lwzu, lwzux,
/// Load word and zero indexed.
///
/// rD() = [ (rA()|0) + rB() ] i.e. if rA() is 0 then the value 0 is used, not the contents of r0.
lwzx,
mcrf, mcrfs, mcrxr,
mfcr, mffsx, mfmsr, mfspr, mfsr, mfsrin, mtcrf, mtfsb0x, mtfsb1x, mtfsfx,
mtfsfix, mtmsr, mtspr, mtsr, mtsrin, mulhwx, mulhwux, mulli, mullwx,
nandx, negx, norx, orx, orcx, ori, oris, rfi, rlwimix, rlwinmx, rlwnmx,

52
OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm
View File

@ -53,6 +53,16 @@ using namespace InstructionSet::PowerPC;
NSAssert(FALSE, @"Didn't handle %@", line);
break;
case Operation::lwzx: {
XCTAssertEqualObjects(operation, @"lwzx");
NSString *const rA = instruction.rA() ? [NSString stringWithFormat:@"r%d", instruction.rA()] : @"0";
NSString *const rB = [NSString stringWithFormat:@"r%d", instruction.rB()];
NSString *const rD = [NSString stringWithFormat:@"r%d", instruction.rD()];
XCTAssertEqualObjects(rD, columns[3]);
XCTAssertEqualObjects(rA, columns[4]);
XCTAssertEqualObjects(rB, columns[5]);
} break;
case Operation::bcx:
case Operation::bclrx:
case Operation::bcctrx: {
@ -62,7 +72,7 @@ using namespace InstructionSet::PowerPC;
switch(instruction.branch_options()) {
case BranchOption::Always: baseOperation = @"b"; break;
case BranchOption::Dec_Zero: baseOperation = @"bdz"; break;
case BranchOption::Dec_NotZero: baseOperation = @"bdnz"; break;
case BranchOption::Dec_NotZero: baseOperation = @"bdnz"; break;
case BranchOption::Clear:
switch(Condition(instruction.bi() & 3)) {
@ -166,46 +176,6 @@ using namespace InstructionSet::PowerPC;
}
} break;
/* case Operation::bcx: {
NSString *expectedOperation;
switch(instruction.branch_options()) {
case BranchOption::Always: expectedOperation = @"b"; break;
case BranchOption::Set:
switch(Condition(instruction.bi() & 3)) {
default: break;
case Condition::Negative: expectedOperation = @"blt"; break;
case Condition::Positive: expectedOperation = @"bgt"; break;
case Condition::Zero: expectedOperation = @"beq"; break;
case Condition::SummaryOverflow: expectedOperation = @"bso"; break;
}
break;
case BranchOption::Clear:
switch(Condition(instruction.bi() & 3)) {
default: break;
case Condition::Negative: expectedOperation = @"bge"; break;
case Condition::Positive: expectedOperation = @"ble"; break;
case Condition::Zero: expectedOperation = @"bne"; break;
case Condition::SummaryOverflow: expectedOperation = @"bns"; break;
}
break;
default:
NSLog(@"No opcode tested for bcx with bo %02x [%@]", instruction.bo(), line);
break;
}
if(instruction.lk()) {
expectedOperation = [expectedOperation stringByAppendingString:@"l"];
}
if(instruction.branch_prediction_hint()) {
expectedOperation = [expectedOperation stringByAppendingString:@"+"];
}
XCTAssertEqualObjects(operation, expectedOperation);
const uint32_t destination = uint32_t(std::strtol([columns[3] UTF8String], 0, 16));
const uint32_t decoded_destination = instruction.bd() + address;
XCTAssertEqual(decoded_destination, destination);
} break;*/
case Operation::bx: {
switch((instruction.aa() ? 2 : 0) | (instruction.lk() ? 1 : 0)) {
case 0: XCTAssertEqualObjects(operation, @"b"); break;