mirror of
https://github.com/TomHarte/CLK.git
synced 2024-06-30 22:29:56 +00:00
Advance CMOS/I2C to a seemingly-valid read.
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parent
9078fc994b
commit
342d90c929
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@ -24,7 +24,7 @@ void Bus::set_data(bool pulled) {
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bool Bus::data() {
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bool Bus::data() {
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bool result = data_;
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bool result = data_;
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if(peripheral_bits_) {
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if(peripheral_bits_) {
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result |= !(peripheral_response_ & 0x80);
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result |= !(peripheral_response_ & 0x200);
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}
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}
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return result;
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return result;
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}
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}
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@ -41,35 +41,33 @@ void Bus::set_clock_data(bool clock_pulled, bool data_pulled) {
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return;
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return;
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}
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}
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auto info = logger.info();
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info.append("C:%d D:%d; ", clock_, data_);
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const bool prior_data = data_;
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const bool prior_data = data_;
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clock_ = clock_pulled;
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clock_ = clock_pulled;
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data_ = data_pulled;
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data_ = data_pulled;
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if(clock_) {
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if(clock_) {
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info.append("nothing");
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return;
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return;
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}
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}
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if(prior_data != data_) {
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if(prior_data != data_) {
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if(data_) {
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if(data_) {
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info.append("start");
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logger.info().append("S");
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signal(Event::Start);
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signal(Event::Start);
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} else {
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} else {
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info.append("stop");
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logger.info().append("P");
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signal(Event::Stop);
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signal(Event::Stop);
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}
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}
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} else {
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} else {
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--peripheral_bits_;
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if(peripheral_bits_) {
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peripheral_response_ <<= 1;
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--peripheral_bits_;
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peripheral_response_ <<= 1;
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}
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if(data_) {
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if(data_) {
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info.append("zero");
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logger.info().append("0");
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signal(Event::Zero);
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signal(Event::Zero);
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} else {
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} else {
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info.append("one");
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logger.info().append("1");
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signal(Event::One);
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signal(Event::One);
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}
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}
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}
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}
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@ -77,75 +75,95 @@ void Bus::set_clock_data(bool clock_pulled, bool data_pulled) {
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void Bus::signal(Event event) {
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void Bus::signal(Event event) {
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const auto capture_bit = [&]() {
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const auto capture_bit = [&]() {
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if(event == Event::Zero || event == Event::One) {
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input_ = uint16_t((input_ << 1) | (event == Event::Zero ? 0 : 1));
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input_ = uint16_t((input_ << 1) | (event == Event::Zero ? 0 : 1));
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++input_count_;
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++input_count_;
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};
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const auto acknowledge = [&]() {
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// Post an acknowledgement bit.
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peripheral_response_ = 0;
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peripheral_bits_ = 2;
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};
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const auto set_state = [&](State state) {
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state_ = state;
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input_count_ = 0;
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input_ = 0;
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};
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const auto enqueue = [&](std::optional<uint8_t> next) {
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if(next) {
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peripheral_response_ = *next;
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peripheral_bits_ = 9;
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set_state(State::PostingByte);
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} else {
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acknowledge();
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set_state(State::AwaitingAddress);
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}
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}
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};
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};
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const auto await_byte = [&] {
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// Allow start and stop conditions at any time.
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peripheral_response_ = 0;
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if(event == Event::Start) {
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peripheral_bits_ = 2;
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set_state(State::CollectingAddress);
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phase_ = Phase::AwaitingByte;
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active_peripheral_ = nullptr;
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logger.info().append("Waiting for byte");
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return;
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};
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// Check for stop condition at any time.
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// "A LOW-to-HIGH transition of the data line
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// while the clock is HIGH is defined as the STOP condition".
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if(event == Event::Stop) {
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logger.info().append("Stopped");
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phase_ = Phase::AwaitingStart;
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}
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}
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switch(phase_) {
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if(event == Event::Stop) {
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case Phase::AwaitingStart:
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set_state(State::AwaitingAddress);
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// "A HIGH-to-LOW transition of the data line while
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if(active_peripheral_) {
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// the clock is HIGH is defined as the START condition"
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active_peripheral_->stop();
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if(event == Event::Start) {
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}
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phase_ = Phase::CollectingAddress;
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active_peripheral_ = nullptr;
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input_count_ = 0;
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return;
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input_ = 0;
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}
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logger.info().append("Waiting for [remainder of] address");
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}
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break;
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case Phase::CollectingAddress:
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switch(state_) {
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case State::AwaitingAddress: break;
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case State::CollectingAddress:
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capture_bit();
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capture_bit();
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if(input_count_ == 8) {
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logger.info().append("Addressed %02x with %s?", uint8_t(input_) & 0xfe, input_ & 1 ? "read" : "write");
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if(input_count_ == 8) {
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auto pair = peripherals_.find(uint8_t(input_) & 0xfe);
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auto pair = peripherals_.find(uint8_t(input_) & 0xfe);
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if(pair != peripherals_.end()) {
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if(pair != peripherals_.end()) {
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active_peripheral_ = pair->second;
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active_peripheral_ = pair->second;
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active_peripheral_->start(input_ & 1);
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await_byte();
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if(input_&1) {
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enqueue(active_peripheral_->read());
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} else {
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acknowledge();
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set_state(State::ReceivingByte);
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}
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} else {
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} else {
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phase_ = Phase::AwaitingStart;
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state_ = State::AwaitingAddress;
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logger.info().append("No device; not acknowledging");
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}
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}
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}
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}
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break;
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break;
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case Phase::AwaitingByte:
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case State::ReceivingByte:
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// Run down the clock on the acknowledge bit.
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// Run down the clock on the acknowledge bit.
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if(peripheral_bits_) {
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if(peripheral_bits_) {
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return;
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return;
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}
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}
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logger.info().append("Beginning byte");
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phase_ = Phase::CollectingByte;
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input_count_ = 0;
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[[fallthrough]];
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case Phase::CollectingByte:
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capture_bit();
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capture_bit();
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if(input_count_ == 8) {
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if(input_count_ == 8) {
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logger.info().append("Got byte %02x?", uint8_t(input_));
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active_peripheral_->write(static_cast<uint8_t>(input_));
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acknowledge();
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await_byte();
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set_state(State::ReceivingByte);
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}
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}
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break;
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break;
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case State::PostingByte:
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// Finish whatever is enqueued.
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if(peripheral_bits_) {
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return;
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}
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enqueue(active_peripheral_->read());
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break;
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}
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}
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}
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}
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@ -9,14 +9,18 @@
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#pragma once
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#pragma once
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#include <cstdint>
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#include <cstdint>
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#include <optional>
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#include <unordered_map>
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#include <unordered_map>
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namespace I2C {
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namespace I2C {
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/// Provides the virtual interface for an I2C peripheral; attaching this to a bus
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/// Provides the virtual interface for an I2C peripheral; attaching this to a bus
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/// provides automatic protocol handling.
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/// provides automatic protocol handling.
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class Peripheral {
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struct Peripheral {
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virtual void start([[maybe_unused]] bool is_read) {}
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virtual void stop() {}
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virtual std::optional<uint8_t> read() { return std::nullopt; }
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virtual void write(uint8_t) {}
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};
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};
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class Bus {
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class Bus {
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@ -48,12 +52,13 @@ private:
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};
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};
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void signal(Event);
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void signal(Event);
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enum class Phase {
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enum class State {
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AwaitingStart,
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AwaitingAddress,
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CollectingAddress,
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CollectingAddress,
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AwaitingByte,
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CollectingByte,
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PostingByte,
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} phase_ = Phase::AwaitingStart;
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ReceivingByte,
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} state_ = State::AwaitingAddress;
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};
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};
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}
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}
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@ -13,7 +13,25 @@
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namespace Archimedes {
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namespace Archimedes {
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struct CMOSRAM: public I2C::Peripheral {
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struct CMOSRAM: public I2C::Peripheral {
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// All TODO.
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void start(bool is_read) override {
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expecting_address_ = !is_read;
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}
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std::optional<uint8_t> read() override {
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return 0;
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}
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void write(uint8_t value) override {
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if(expecting_address_) {
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address_ = value;
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} else {
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// TODO: write to RAM.
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}
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}
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private:
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bool expecting_address_ = false;
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uint8_t address_;
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};
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};
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}
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}
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