From 3c1c4f89e93b873b22d17e4f027465591b810e74 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 22 May 2022 08:02:32 -0400
Subject: [PATCH] Add MULU/S functionality, though not timing.

---
 .../Implementation/68000Mk2Implementation.hpp | 29 +++++++++++++++++++
 .../Implementation/68000Mk2Storage.hpp        |  4 +--
 2 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
index f4a34e39a..38f0372ac 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -162,6 +162,7 @@ enum ExecutionState: int {
 	MOVEMtoM_finish,
 
 	DIVU_DIVS,
+	MULU_MULS,
 };
 
 // MARK: - The state machine.
@@ -697,6 +698,8 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 
 				StdCASE(DIVU,		perform_state_ = DIVU_DIVS);
 				StdCASE(DIVS,		perform_state_ = DIVU_DIVS);
+				StdCASE(MULU,		perform_state_ = MULU_MULS);
+				StdCASE(MULS,		perform_state_ = MULU_MULS);
 
 				default:
 					assert(false);
@@ -1854,6 +1857,24 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Prefetch();		// np
 		MoveToStateSpecific(Decode);
 
+		//
+		// MULU and MULS
+		//
+		BeginState(MULU_MULS):
+			Prefetch();		// np
+
+			// Perform the instruction.
+			PerformDynamic();
+
+			// Delay the correct amount of time.
+			IdleBus(dynamic_instruction_length_);
+
+			// MULU and MULS are always to a register, so just write back here
+			// to save on dispatch costs.
+			registers_[instruction_.reg(1)] = operand_[1];
+
+		MoveToStateSpecific(Decode);
+
 		//
 		// Various states TODO.
 		//
@@ -1951,6 +1972,14 @@ template <bool did_overflow> void ProcessorBase::did_divs(int32_t, int32_t) {
 	// TODO: calculate cost.
 }
 
+template <typename IntT> void ProcessorBase::did_mulu(IntT) {
+	// TODO: calculate cost.
+}
+
+template <typename IntT> void ProcessorBase::did_muls(IntT) {
+	// TODO: calculate cost.
+}
+
 template <bool use_current_instruction_pc> void ProcessorBase::raise_exception(int vector) {
 	// No overt action is taken here; instructions that might throw an exception are required
 	// to check-in after the fact.
diff --git a/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp b/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
index 6de709794..221e98373 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
@@ -122,8 +122,8 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
 
 	// Flow controller... many TODO.
 	using Preinstruction = InstructionSet::M68k::Preinstruction;
-	template <typename IntT> void did_mulu(IntT) {}		//
-	template <typename IntT> void did_muls(IntT) {}		//
+	template <typename IntT> void did_mulu(IntT);
+	template <typename IntT> void did_muls(IntT);
 	inline void did_chk(bool, bool);
 	inline void did_scc(bool);
 	inline void did_shift(int) {}						//