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With a very basic stab at something a bit like the memory map (sans paging), execution begins.
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@ -20,6 +20,40 @@ HalfCycles Machine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &c
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clock_offset_ = (clock_offset_ + cycle.length) & HalfCycles(7);
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set_wait_line(clock_offset_ >= HalfCycles(2));
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// Stop now if no action is strictly required.
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if(!cycle.is_terminal()) return HalfCycles(0);
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uint16_t address = cycle.address ? *cycle.address : 0x0000;
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switch(cycle.operation) {
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case CPU::Z80::PartialMachineCycle::ReadOpcode:
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case CPU::Z80::PartialMachineCycle::Read:
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switch(address >> 14) {
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case 0: *cycle.value = os_[address & 16383]; break;
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case 1: case 2:
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*cycle.value = ram_[address];
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break;
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case 3: *cycle.value = basic_[address & 16383]; break;
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}
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break;
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case CPU::Z80::PartialMachineCycle::Write:
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ram_[address] = *cycle.value;
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break;
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case CPU::Z80::PartialMachineCycle::Output:
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printf("Output %02x -> %04x?\n", *cycle.value, address);
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break;
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case CPU::Z80::PartialMachineCycle::Input:
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printf("Input %04x?\n", address);
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break;
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case CPU::Z80::PartialMachineCycle::Interrupt:
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*cycle.value = 0xff;
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break;
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default: break;
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}
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return HalfCycles(0);
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}
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@ -27,6 +61,12 @@ void Machine::flush() {
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}
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void Machine::set_rom(ROMType type, std::vector<uint8_t> data) {
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// Keep only the two ROMs that are currently of interest.
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switch(type) {
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case ROMType::OS464: os_ = data; break;
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case ROMType::BASIC464: basic_ = data; break;
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default: break;
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}
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}
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void Machine::setup_output(float aspect_ratio) {
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@ -48,6 +48,9 @@ class Machine:
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private:
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std::shared_ptr<Outputs::CRT::CRT> crt_;
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HalfCycles clock_offset_;
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uint8_t ram_[65536];
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std::vector<uint8_t> os_, basic_;
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};
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}
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