diff --git a/InstructionSets/x86/Implementation/LoadStore.hpp b/InstructionSets/x86/Implementation/LoadStore.hpp
index e8bfe8a13..a2086f828 100644
--- a/InstructionSets/x86/Implementation/LoadStore.hpp
+++ b/InstructionSets/x86/Implementation/LoadStore.hpp
@@ -77,4 +77,12 @@ void mov(
 	destination = source;
 }
 
+template <typename ContextT>
+void smsw(
+	write_t<uint16_t> destination,
+	ContextT &context
+) {
+	destination = context.registers.msw();
+}
+
 }
diff --git a/InstructionSets/x86/Implementation/PerformImplementation.hpp b/InstructionSets/x86/Implementation/PerformImplementation.hpp
index 0e14ba949..d91fe0e50 100644
--- a/InstructionSets/x86/Implementation/PerformImplementation.hpp
+++ b/InstructionSets/x86/Implementation/PerformImplementation.hpp
@@ -282,6 +282,13 @@ template <
 				context.segments.did_update(instruction.destination().source());
 			}
 		break;
+		case Operation::SMSW:
+			if constexpr (ContextT::model >= Model::i80286 && std::is_same_v<IntT, uint16_t>) {
+				Primitive::smsw(destination_w(), context);
+			} else {
+				assert(false);
+			}
+		break;
 
 		case Operation::JO:		jcc(context.flags.template condition<Condition::Overflow>());		return;
 		case Operation::JNO:	jcc(!context.flags.template condition<Condition::Overflow>());		return;
diff --git a/Machines/PCCompatible/Registers.hpp b/Machines/PCCompatible/Registers.hpp
index 49e64a518..608b6ed0b 100644
--- a/Machines/PCCompatible/Registers.hpp
+++ b/Machines/PCCompatible/Registers.hpp
@@ -18,68 +18,77 @@ struct Registers;
 
 template <>
 struct Registers<InstructionSet::x86::Model::i8086> {
-	public:
-		static constexpr bool is_32bit = false;
+public:
+	static constexpr bool is_32bit = false;
 
-		uint8_t &al()	{	return ax_.halves.low;	}
-		uint8_t &ah()	{	return ax_.halves.high;	}
-		uint16_t &ax()	{	return ax_.full;		}
+	uint8_t &al()	{	return ax_.halves.low;	}
+	uint8_t &ah()	{	return ax_.halves.high;	}
+	uint16_t &ax()	{	return ax_.full;		}
 
-		CPU::RegisterPair16 &axp()	{	return ax_;	}
+	CPU::RegisterPair16 &axp()	{	return ax_;	}
 
-		uint8_t &cl()	{	return cx_.halves.low;	}
-		uint8_t &ch()	{	return cx_.halves.high;	}
-		uint16_t &cx()	{	return cx_.full;		}
+	uint8_t &cl()	{	return cx_.halves.low;	}
+	uint8_t &ch()	{	return cx_.halves.high;	}
+	uint16_t &cx()	{	return cx_.full;		}
 
-		uint8_t &dl()	{	return dx_.halves.low;	}
-		uint8_t &dh()	{	return dx_.halves.high;	}
-		uint16_t &dx()	{	return dx_.full;		}
+	uint8_t &dl()	{	return dx_.halves.low;	}
+	uint8_t &dh()	{	return dx_.halves.high;	}
+	uint16_t &dx()	{	return dx_.full;		}
 
-		uint8_t &bl()	{	return bx_.halves.low;	}
-		uint8_t &bh()	{	return bx_.halves.high;	}
-		uint16_t &bx()	{	return bx_.full;		}
+	uint8_t &bl()	{	return bx_.halves.low;	}
+	uint8_t &bh()	{	return bx_.halves.high;	}
+	uint16_t &bx()	{	return bx_.full;		}
 
-		uint16_t &sp()	{	return sp_;				}
-		uint16_t &bp()	{	return bp_;				}
-		uint16_t &si()	{	return si_;				}
-		uint16_t &di()	{	return di_;				}
+	uint16_t &sp()	{	return sp_;				}
+	uint16_t &bp()	{	return bp_;				}
+	uint16_t &si()	{	return si_;				}
+	uint16_t &di()	{	return di_;				}
 
-		uint16_t &ip()	{	return ip_;				}
+	uint16_t &ip()	{	return ip_;				}
 
-		uint16_t &es()		{	return es_;			}
-		uint16_t &cs()		{	return cs_;			}
-		uint16_t &ds()		{	return ds_;			}
-		uint16_t &ss()		{	return ss_;			}
-		uint16_t es() const	{	return es_;			}
-		uint16_t cs() const	{	return cs_;			}
-		uint16_t ds() const	{	return ds_;			}
-		uint16_t ss() const	{	return ss_;			}
+	uint16_t &es()		{	return es_;			}
+	uint16_t &cs()		{	return cs_;			}
+	uint16_t &ds()		{	return ds_;			}
+	uint16_t &ss()		{	return ss_;			}
+	uint16_t es() const	{	return es_;			}
+	uint16_t cs() const	{	return cs_;			}
+	uint16_t ds() const	{	return ds_;			}
+	uint16_t ss() const	{	return ss_;			}
 
-		void reset() {
-			cs_ = 0xffff;
-			ip_ = 0;
-		}
+	void reset() {
+		cs_ = 0xffff;
+		ip_ = 0;
+	}
 
-	private:
-		CPU::RegisterPair16 ax_;
-		CPU::RegisterPair16 cx_;
-		CPU::RegisterPair16 dx_;
-		CPU::RegisterPair16 bx_;
+private:
+	CPU::RegisterPair16 ax_;
+	CPU::RegisterPair16 cx_;
+	CPU::RegisterPair16 dx_;
+	CPU::RegisterPair16 bx_;
 
-		uint16_t sp_;
-		uint16_t bp_;
-		uint16_t si_;
-		uint16_t di_;
-		uint16_t es_, cs_, ds_, ss_;
-		uint16_t ip_;
+	uint16_t sp_;
+	uint16_t bp_;
+	uint16_t si_;
+	uint16_t di_;
+	uint16_t es_, cs_, ds_, ss_;
+	uint16_t ip_;
 };
 
 template <>
-struct Registers<InstructionSet::x86::Model::i80186>: public Registers<InstructionSet::x86::Model::i8086> {
-};
+struct Registers<InstructionSet::x86::Model::i80186>: public Registers<InstructionSet::x86::Model::i8086> {};
 
 template <>
 struct Registers<InstructionSet::x86::Model::i80286>: public Registers<InstructionSet::x86::Model::i80186> {
+public:
+	void reset() {
+		Registers<InstructionSet::x86::Model::i80186>::reset();
+		machine_status_ = 0;
+	}
+
+	uint16_t msw() const {	return machine_status_;	}
+
+private:
+	uint16_t machine_status_;
 };
 
 }