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Some minor style changes, plus I think I've talked myself into an expanded Operation-tracking enum. Probably.
This commit is contained in:
Thomas Harte
parent
9aeb6ee532
commit
3d5986c55d
@ -41,7 +41,7 @@ template <Operation operation> Preinstruction Predecoder::decode(uint16_t instru
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//
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// MARK: ABCD, SBCD.
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//
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case Operation::ABCD: case Operation::SBCD: {
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case Operation::ABCD: case Operation::SBCD: {
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const auto addressing_mode = (instruction & 8) ?
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AddressingMode::AddressRegisterIndirectWithPredecrement : AddressingMode::DataRegisterDirect;
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@ -55,7 +55,7 @@ template <Operation operation> Preinstruction Predecoder::decode(uint16_t instru
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//
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case Operation::ANDb: case Operation::ANDw: case Operation::ANDl:
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case Operation::ORb: case Operation::ORw: case Operation::ORl:
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case Operation::EORb: case Operation::EORw: case Operation::EORl: {
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case Operation::EORb: case Operation::EORw: case Operation::EORl: {
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// Opmode 7 is illegal.
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if(opmode == 7) {
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return Preinstruction();
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@ -99,7 +99,7 @@ template <Operation operation> Preinstruction Predecoder::decode(uint16_t instru
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//
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case Operation::EXG:
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switch((instruction >> 3)&31) {
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default: return Preinstruction();
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default: return Preinstruction();
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case 0x08: return Preinstruction(operation,
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AddressingMode::DataRegisterDirect, ea_register,
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@ -127,7 +127,38 @@ template <Operation operation> Preinstruction Predecoder::decode(uint16_t instru
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ea_combined_mode, ea_register,
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AddressingMode::DataRegisterDirect, data_register);
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//
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// MARK: ORItoCCR, ORItoSR, ANDItoCCR, ANDItoSR, EORItoCCR, EORItoSR
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//
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case Operation::ORItoSR: case Operation::ORItoCCR:
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case Operation::ANDItoSR: case Operation::ANDItoCCR:
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case Operation::EORItoSR: case Operation::EORItoCCR:
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return Preinstruction(operation,
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AddressingMode::ImmediateData, 0,
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operation == Operation::ORItoSR || operation == Operation::ANDItoSR || operation == Operation::EORItoSR);
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//
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// MARK: MOVEPtoRw, MOVEPtoRl
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//
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case Operation::MOVEPtoRw: case Operation::MOVEPtoRl:
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return Preinstruction(operation,
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AddressingMode::AddressRegisterIndirectWithDisplacement, ea_register,
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AddressingMode::DataRegisterDirect, data_register);
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case Operation::MOVEPtoMw: case Operation::MOVEPtoMl:
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return Preinstruction(operation,
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AddressingMode::DataRegisterDirect, data_register,
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AddressingMode::AddressRegisterIndirectWithDisplacement, ea_register);
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// TODO: there's no need for separate toR and toM given that source and dest are specified overtly.
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// Between this and the ANDI/etc case, probably this template needs to take a type other than Operation?
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// That'll be a slight hassle because it couldn't inherit from Operation and therefore would either need
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// to duplicate it or in some potentially-fragile way avoid collisions with it. Not to mention all the
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// casting that'd have to be around. So probably duplicate?
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//
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// MARK: Impossible error case.
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//
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default:
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// Should be unreachable.
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assert(false);
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@ -142,71 +173,73 @@ template <Operation operation> Preinstruction Predecoder::decode(uint16_t instru
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// MARK: - Page decoders.
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Preinstruction Predecoder::decode0(uint16_t instruction) {
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switch(instruction) {
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case 0x003c: return decode<Operation::ORItoCCR>(instruction);
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case 0x007c: return decode<Operation::ORItoSR>(instruction);
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case 0x023c: return decode<Operation::ANDItoCCR>(instruction);
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case 0x027c: return decode<Operation::ANDItoSR>(instruction);
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case 0x0a3c: return decode<Operation::EORItoCCR>(instruction);
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case 0x0a7c: return decode<Operation::EORItoSR>(instruction);
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switch(instruction & 0xfff) {
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case 0x03c: return decode<Operation::ORItoCCR>(instruction); // 4-155 (p259)
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case 0x07c: return decode<Operation::ORItoSR>(instruction); // 6-27 (p646)
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case 0x23c: return decode<Operation::ANDItoCCR>(instruction); // 4-20 (p124)
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case 0x27c: return decode<Operation::ANDItoSR>(instruction); // 6-2 (p456)
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case 0xa3c: return decode<Operation::EORItoCCR>(instruction); // 4-104 (p208)
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case 0xa7c: return decode<Operation::EORItoSR>(instruction); // 6-10 (p464)
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default: break;
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default: break;
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}
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// TODO: determine whether it's useful to be able to flag these as immediate
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// versions here, rather than having it determined dynamically in decode.
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switch(instruction & 0xfc0) {
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// 4-153 (p257)
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case 0x000: return decode<Operation::ORb>(instruction);
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case 0x040: return decode<Operation::ORw>(instruction);
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case 0x080: return decode<Operation::ORl>(instruction);
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case 0x000: return decode<Operation::ORb>(instruction);
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case 0x040: return decode<Operation::ORw>(instruction);
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case 0x080: return decode<Operation::ORl>(instruction);
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// 4-18 (p122)
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case 0x200: return decode<Operation::ANDb>(instruction);
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case 0x240: return decode<Operation::ANDw>(instruction);
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case 0x280: return decode<Operation::ANDl>(instruction);
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case 0x200: return decode<Operation::ANDb>(instruction);
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case 0x240: return decode<Operation::ANDw>(instruction);
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case 0x280: return decode<Operation::ANDl>(instruction);
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// 4-179 (p283)
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case 0x400: return decode<Operation::SUBb>(instruction);
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case 0x440: return decode<Operation::SUBw>(instruction);
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case 0x480: return decode<Operation::SUBl>(instruction);
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case 0x400: return decode<Operation::SUBb>(instruction);
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case 0x440: return decode<Operation::SUBw>(instruction);
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case 0x480: return decode<Operation::SUBl>(instruction);
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// 4-9 (p113)
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case 0x600: return decode<Operation::ADDb>(instruction);
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case 0x640: return decode<Operation::ADDw>(instruction);
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case 0x680: return decode<Operation::ADDl>(instruction);
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case 0x600: return decode<Operation::ADDb>(instruction);
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case 0x640: return decode<Operation::ADDw>(instruction);
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case 0x680: return decode<Operation::ADDl>(instruction);
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// 4-63 (p167)
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case 0x800: return decode<Operation::BTSTb>(instruction);
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case 0x800: return decode<Operation::BTSTb>(instruction);
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// 4-29 (p133)
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case 0x840: return decode<Operation::BCHGb>(instruction);
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case 0x840: return decode<Operation::BCHGb>(instruction);
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// 4-32 (p136)
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case 0x880: return decode<Operation::BCLRb>(instruction);
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case 0x880: return decode<Operation::BCLRb>(instruction);
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// 4-58 (p162)
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case 0x8c0: return decode<Operation::BSETb>(instruction);
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case 0x8c0: return decode<Operation::BSETb>(instruction);
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// 4-102 (p206)
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case 0xa00: return decode<Operation::EORb>(instruction);
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case 0xa40: return decode<Operation::EORw>(instruction);
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case 0xa80: return decode<Operation::EORl>(instruction);
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case 0xa00: return decode<Operation::EORb>(instruction);
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case 0xa40: return decode<Operation::EORw>(instruction);
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case 0xa80: return decode<Operation::EORl>(instruction);
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// 4-79 (p183)
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case 0xc00: return decode<Operation::CMPb>(instruction);
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case 0xc40: return decode<Operation::CMPw>(instruction);
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case 0xc80: return decode<Operation::CMPl>(instruction);
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case 0xc00: return decode<Operation::CMPb>(instruction);
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case 0xc40: return decode<Operation::CMPw>(instruction);
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case 0xc80: return decode<Operation::CMPl>(instruction);
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default: break;
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default: break;
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}
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switch(instruction & 0x1c0) {
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case 0x100: return decode<Operation::BTSTb>(instruction); // 4-62 (p166)
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case 0x180: return decode<Operation::BCLRb>(instruction); // 4-31 (p135)
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case 0x100: return decode<Operation::BTSTb>(instruction); // 4-62 (p166)
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case 0x180: return decode<Operation::BCLRb>(instruction); // 4-31 (p135)
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case 0x140: return decode<Operation::BCHGb>(instruction); // 4-28 (p132)
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case 0x1c0: return decode<Operation::BSETb>(instruction); // 4-57 (p161)
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case 0x140: return decode<Operation::BCHGb>(instruction); // 4-28 (p132)
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case 0x1c0: return decode<Operation::BSETb>(instruction); // 4-57 (p161)
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default: break;
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default: break;
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}
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switch(instruction & 0x1f8) {
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@ -216,7 +249,7 @@ Preinstruction Predecoder::decode0(uint16_t instruction) {
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case 0x188: return decode<Operation::MOVEPtoMw>(instruction);
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case 0x1c8: return decode<Operation::MOVEPtoMl>(instruction);
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default: break;
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default: break;
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}
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return Preinstruction();
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@ -242,44 +275,44 @@ Preinstruction Predecoder::decode4(uint16_t instruction) {
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case 0xe75: return decode<Operation::RTS>(instruction); // 4-169 (p273)
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case 0xe76: return decode<Operation::TRAPV>(instruction); // 4-191 (p295)
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case 0xe77: return decode<Operation::RTR>(instruction); // 4-168 (p272)
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default: break;
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default: break;
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}
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switch(instruction & 0xfc0) {
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// 4-146 (p250)
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case 0x000: return decode<Operation::NEGXb>(instruction);
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case 0x040: return decode<Operation::NEGXw>(instruction);
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case 0x080: return decode<Operation::NEGXl>(instruction);
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case 0x000: return decode<Operation::NEGXb>(instruction);
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case 0x040: return decode<Operation::NEGXw>(instruction);
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case 0x080: return decode<Operation::NEGXl>(instruction);
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// 6-17 (p471)
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case 0x0c0: return decode<Operation::MOVEfromSR>(instruction);
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case 0x0c0: return decode<Operation::MOVEfromSR>(instruction);
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// 4-73 (p177)
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case 0x200: return decode<Operation::CLRb>(instruction);
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case 0x240: return decode<Operation::CLRw>(instruction);
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case 0x280: return decode<Operation::CLRl>(instruction);
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case 0x200: return decode<Operation::CLRb>(instruction);
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case 0x240: return decode<Operation::CLRw>(instruction);
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case 0x280: return decode<Operation::CLRl>(instruction);
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// 4-144 (p248)
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case 0x400: return decode<Operation::NEGb>(instruction);
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case 0x440: return decode<Operation::NEGw>(instruction);
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case 0x480: return decode<Operation::NEGl>(instruction);
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case 0x400: return decode<Operation::NEGb>(instruction);
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case 0x440: return decode<Operation::NEGw>(instruction);
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case 0x480: return decode<Operation::NEGl>(instruction);
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// 4-123 (p227)
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case 0x4c0: return decode<Operation::MOVEtoCCR>(instruction);
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case 0x4c0: return decode<Operation::MOVEtoCCR>(instruction);
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// 4-148 (p250)
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case 0x600: return decode<Operation::NOTb>(instruction);
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case 0x640: return decode<Operation::NOTw>(instruction);
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case 0x680: return decode<Operation::NOTl>(instruction);
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case 0x600: return decode<Operation::NOTb>(instruction);
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case 0x640: return decode<Operation::NOTw>(instruction);
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case 0x680: return decode<Operation::NOTl>(instruction);
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// 4-123 (p227)
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case 0x6c0: return decode<Operation::MOVEtoSR>(instruction);
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case 0x6c0: return decode<Operation::MOVEtoSR>(instruction);
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// 4-142 (p246)
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case 0x800: return decode<Operation::NBCD>(instruction);
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case 0x800: return decode<Operation::NBCD>(instruction);
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// 4-159 (p263)
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case 0x840: return decode<Operation::PEA>(instruction);
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case 0x840: return decode<Operation::PEA>(instruction);
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// 4-128 (p232)
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case 0x880: return decode<Operation::MOVEMtoMw>(instruction);
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@ -288,42 +321,42 @@ Preinstruction Predecoder::decode4(uint16_t instruction) {
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case 0xcc0: return decode<Operation::MOVEMtoRl>(instruction);
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// 4-192 (p296)
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case 0xa00: return decode<Operation::TSTb>(instruction);
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case 0xa40: return decode<Operation::TSTw>(instruction);
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case 0xa80: return decode<Operation::TSTl>(instruction);
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case 0xa00: return decode<Operation::TSTb>(instruction);
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case 0xa40: return decode<Operation::TSTw>(instruction);
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case 0xa80: return decode<Operation::TSTl>(instruction);
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// 4-186 (p290)
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case 0xac0: return decode<Operation::TAS>(instruction);
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case 0xac0: return decode<Operation::TAS>(instruction);
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// 4-109 (p213)
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case 0xe80: return decode<Operation::JSR>(instruction);
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case 0xe80: return decode<Operation::JSR>(instruction);
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// 4-108 (p212)
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case 0xec0: return decode<Operation::JMP>(instruction);
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case 0xec0: return decode<Operation::JMP>(instruction);
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default: break;
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default: break;
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}
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switch(instruction & 0x1c0) {
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case 0x1c0: return decode<Operation::MOVEAl>(instruction); // 4-110 (p214)
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case 0x180: return decode<Operation::CHK>(instruction); // 4-69 (p173)
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default: break;
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case 0x1c0: return decode<Operation::MOVEAl>(instruction); // 4-110 (p214)
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case 0x180: return decode<Operation::CHK>(instruction); // 4-69 (p173)
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default: break;
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}
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switch(instruction & 0xff0) {
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case 0xe40: return decode<Operation::TRAP>(instruction); // 4-188 (p292)
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default: break;
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case 0xe40: return decode<Operation::TRAP>(instruction); // 4-188 (p292)
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default: break;
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}
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switch(instruction & 0xff8) {
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case 0x860: return decode<Operation::SWAP>(instruction); // 4-185 (p289)
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case 0x880: return decode<Operation::EXTbtow>(instruction); // 4-106 (p210)
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case 0x8c0: return decode<Operation::EXTwtol>(instruction); // 4-106 (p210)
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case 0xe50: return decode<Operation::LINK>(instruction); // 4-111 (p215)
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case 0xe58: return decode<Operation::UNLINK>(instruction); // 4-194 (p298)
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case 0xe60: return decode<Operation::MOVEtoUSP>(instruction); // 6-21 (p475)
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case 0xe68: return decode<Operation::MOVEfromUSP>(instruction); // 6-21 (p475)
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default: break;
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case 0x860: return decode<Operation::SWAP>(instruction); // 4-185 (p289)
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case 0x880: return decode<Operation::EXTbtow>(instruction); // 4-106 (p210)
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case 0x8c0: return decode<Operation::EXTwtol>(instruction); // 4-106 (p210)
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case 0xe50: return decode<Operation::LINK>(instruction); // 4-111 (p215)
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case 0xe58: return decode<Operation::UNLINK>(instruction); // 4-194 (p298)
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case 0xe60: return decode<Operation::MOVEtoUSP>(instruction); // 6-21 (p475)
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case 0xe68: return decode<Operation::MOVEfromUSP>(instruction); // 6-21 (p475)
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default: break;
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}
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return Preinstruction();
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@ -332,23 +365,23 @@ Preinstruction Predecoder::decode4(uint16_t instruction) {
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Preinstruction Predecoder::decode5(uint16_t instruction) {
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switch(instruction & 0x1c0) {
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// 4-11 (p115)
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case 0x000: return decode<Operation::ADDQb>(instruction);
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case 0x040: return decode<Operation::ADDQw>(instruction);
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case 0x080: return decode<Operation::ADDQl>(instruction);
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case 0x000: return decode<Operation::ADDQb>(instruction);
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case 0x040: return decode<Operation::ADDQw>(instruction);
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case 0x080: return decode<Operation::ADDQl>(instruction);
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// 4-181 (p285)
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case 0x100: return decode<Operation::SUBQb>(instruction);
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case 0x140: return decode<Operation::SUBQw>(instruction);
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case 0x180: return decode<Operation::SUBQl>(instruction);
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case 0x100: return decode<Operation::SUBQb>(instruction);
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case 0x140: return decode<Operation::SUBQw>(instruction);
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case 0x180: return decode<Operation::SUBQl>(instruction);
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default: break;
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default: break;
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}
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switch(instruction & 0x0c0) {
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// 4-173 (p276), though this'll also hit DBcc 4-91 (p195)
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case 0x0c0: return decode<Operation::Scc>(instruction);
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case 0x0c0: return decode<Operation::Scc>(instruction);
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default: break;
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default: break;
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}
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return Preinstruction();
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}
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@ -372,13 +405,13 @@ Preinstruction Predecoder::decode8(uint16_t instruction) {
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case 0x00: return decode<Operation::ORb>(instruction);
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case 0x40: return decode<Operation::ORw>(instruction);
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case 0x80: return decode<Operation::ORl>(instruction);
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default: break;
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default: break;
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}
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switch(instruction & 0x1c0) {
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case 0x0c0: return decode<Operation::DIVU>(instruction); // 4-97 (p201)
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case 0x1c0: return decode<Operation::DIVS>(instruction); // 4-93 (p197)
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default: break;
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default: break;
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}
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return Preinstruction();
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@ -391,7 +424,7 @@ Preinstruction Predecoder::decode9(uint16_t instruction) {
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case 0x40: return decode<Operation::SUBw>(instruction);
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case 0x80: return decode<Operation::SUBl>(instruction);
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default: break;
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default: break;
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}
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switch(instruction & 0x1c0) {
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@ -399,7 +432,7 @@ Preinstruction Predecoder::decode9(uint16_t instruction) {
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case 0x0c0: return decode<Operation::SUBAw>(instruction);
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case 0x1c0: return decode<Operation::SUBAl>(instruction);
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default: break;
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default: break;
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}
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switch(instruction & 0x1f0) {
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@ -408,7 +441,7 @@ Preinstruction Predecoder::decode9(uint16_t instruction) {
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case 0x140: return decode<Operation::SUBXw>(instruction);
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case 0x180: return decode<Operation::SUBXl>(instruction);
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default: break;
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default: break;
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}
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return Preinstruction();
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@ -424,7 +457,7 @@ Preinstruction Predecoder::decodeB(uint16_t instruction) {
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case 0x000: return decode<Operation::EORb>(instruction);
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case 0x040: return decode<Operation::EORw>(instruction);
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case 0x080: return decode<Operation::EORl>(instruction);
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default: break;
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default: break;
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}
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switch(instruction & 0x1c0) {
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@ -437,7 +470,7 @@ Preinstruction Predecoder::decodeB(uint16_t instruction) {
|
||||
case 0x0c0: return decode<Operation::CMPAw>(instruction);
|
||||
case 0x1c0: return decode<Operation::CMPAl>(instruction);
|
||||
|
||||
default: break;
|
||||
default: break;
|
||||
}
|
||||
|
||||
return Preinstruction();
|
||||
@ -445,8 +478,8 @@ Preinstruction Predecoder::decodeB(uint16_t instruction) {
|
||||
|
||||
Preinstruction Predecoder::decodeC(uint16_t instruction) {
|
||||
switch(instruction & 0x1f0) {
|
||||
case 0x100: return decode<Operation::ABCD>(instruction); // 4-3 (p107)
|
||||
default: break;
|
||||
case 0x100: return decode<Operation::ABCD>(instruction); // 4-3 (p107)
|
||||
default: break;
|
||||
}
|
||||
|
||||
switch(instruction & 0x0c0) {
|
||||
@ -454,13 +487,13 @@ Preinstruction Predecoder::decodeC(uint16_t instruction) {
|
||||
case 0x00: return decode<Operation::ANDb>(instruction);
|
||||
case 0x40: return decode<Operation::ANDw>(instruction);
|
||||
case 0x80: return decode<Operation::ANDl>(instruction);
|
||||
default: break;
|
||||
default: break;
|
||||
}
|
||||
|
||||
switch(instruction & 0x1c0) {
|
||||
case 0x0c0: return decode<Operation::MULU>(instruction); // 4-139 (p243)
|
||||
case 0x1c0: return decode<Operation::MULS>(instruction); // 4-136 (p240)
|
||||
default: break;
|
||||
default: break;
|
||||
}
|
||||
|
||||
// 4-105 (p209)
|
||||
@ -468,7 +501,7 @@ Preinstruction Predecoder::decodeC(uint16_t instruction) {
|
||||
case 0x140:
|
||||
case 0x148:
|
||||
case 0x188: return decode<Operation::EXG>(instruction);
|
||||
default: break;
|
||||
default: break;
|
||||
}
|
||||
|
||||
return Preinstruction();
|
||||
@ -481,7 +514,7 @@ Preinstruction Predecoder::decodeD(uint16_t instruction) {
|
||||
case 0x040: return decode<Operation::ADDw>(instruction);
|
||||
case 0x080: return decode<Operation::ADDl>(instruction);
|
||||
|
||||
default: break;
|
||||
default: break;
|
||||
}
|
||||
|
||||
switch(instruction & 0x1c0) {
|
||||
@ -489,7 +522,7 @@ Preinstruction Predecoder::decodeD(uint16_t instruction) {
|
||||
case 0x0c0: return decode<Operation::ADDAw>(instruction);
|
||||
case 0x1c0: return decode<Operation::ADDAl>(instruction);
|
||||
|
||||
default: break;
|
||||
default: break;
|
||||
}
|
||||
|
||||
switch(instruction & 0x1f0) {
|
||||
@ -498,7 +531,7 @@ Preinstruction Predecoder::decodeD(uint16_t instruction) {
|
||||
case 0x140: return decode<Operation::ADDXw>(instruction);
|
||||
case 0x180: return decode<Operation::ADDXl>(instruction);
|
||||
|
||||
default: break;
|
||||
default: break;
|
||||
}
|
||||
|
||||
return Preinstruction();
|
||||
@ -546,7 +579,7 @@ Preinstruction Predecoder::decodeE(uint16_t instruction) {
|
||||
case 0x158: return decode<Operation::ROLw>(instruction);
|
||||
case 0x198: return decode<Operation::ROLl>(instruction);
|
||||
|
||||
default: break;
|
||||
default: break;
|
||||
}
|
||||
|
||||
switch(instruction & 0xfc0) {
|
||||
@ -559,7 +592,7 @@ Preinstruction Predecoder::decodeE(uint16_t instruction) {
|
||||
case 0x6c0: return decode<Operation::RORm>(instruction); // 4-160 (p264)
|
||||
case 0x7c0: return decode<Operation::ROLm>(instruction); // 4-160 (p264)
|
||||
|
||||
default: break;
|
||||
default: break;
|
||||
}
|
||||
|
||||
return Preinstruction();
|
||||
@ -591,7 +624,7 @@ Preinstruction Predecoder::decode(uint16_t instruction) {
|
||||
case 0xe000: return decodeE(instruction);
|
||||
case 0xf000: return decodeF(instruction);
|
||||
|
||||
default: break;
|
||||
default: break;
|
||||
}
|
||||
|
||||
return Preinstruction();
|
||||
|
||||
@ -131,7 +131,7 @@ enum class AddressingMode: uint8_t {
|
||||
DataRegisterDirect = 0b00'000,
|
||||
|
||||
/// An
|
||||
AddressRegisterDirect = 0b11'000,
|
||||
AddressRegisterDirect = 0b00'001,
|
||||
/// (An)
|
||||
AddressRegisterIndirect = 0b00'010,
|
||||
/// (An)+
|
||||
@ -213,12 +213,21 @@ class Preinstruction {
|
||||
Preinstruction(
|
||||
Operation operation,
|
||||
AddressingMode op1_mode, int op1_reg,
|
||||
AddressingMode op2_mode, int op2_reg) : operation(operation)
|
||||
AddressingMode op2_mode, int op2_reg,
|
||||
[[maybe_unused]] bool is_supervisor = false) : operation(operation)
|
||||
{
|
||||
operands_[0] = uint8_t(op1_mode) | uint8_t(op1_reg << 5);
|
||||
operands_[1] = uint8_t(op2_mode) | uint8_t(op2_reg << 5);
|
||||
}
|
||||
|
||||
Preinstruction(Operation operation, [[maybe_unused]] bool is_supervisor = false) : operation(operation) {}
|
||||
|
||||
Preinstruction(Operation operation, AddressingMode op1_mode, int op1_reg, [[maybe_unused]] bool is_supervisor = false) : operation(operation) {
|
||||
operands_[0] = uint8_t(op1_mode) | uint8_t(op1_reg << 5);
|
||||
}
|
||||
|
||||
// TODO: record is_supervisor.
|
||||
|
||||
Preinstruction() {}
|
||||
};
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user