From 3da1b3bf9bb3b5407cd005eea7f86e1594a145d0 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Mon, 29 Apr 2019 19:22:05 -0400
Subject: [PATCH] Introduces storage for various bus inputs.

---
 Processors/68000/68000.hpp                    | 27 ++++++++++++++-----
 .../68000/Implementation/68000Storage.hpp     |  9 ++++++-
 2 files changed, 29 insertions(+), 7 deletions(-)

diff --git a/Processors/68000/68000.hpp b/Processors/68000/68000.hpp
index b230c5a69..34b0c0760 100644
--- a/Processors/68000/68000.hpp
+++ b/Processors/68000/68000.hpp
@@ -217,26 +217,41 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform = false> cla
 		void run_for(HalfCycles duration);
 
 		using State = ProcessorState;
+		/// @returns The current processor state.
 		State get_state();
+
+		/// Sets the processor to the supplied state.
 		void set_state(const State &);
 
 		/// Sets the DTack line — @c true for active, @c false for inactive.
-		void set_dtack(bool);
+		inline void set_dtack(bool dtack) {
+			dtack_ = dtack;
+		}
 
 		/// Sets the VPA (valid peripheral address) line — @c true for active, @c false for inactive.
-		void set_is_peripheral_address(bool);
+		inline void set_is_peripheral_address(bool is_peripheral_address) {
+			is_peripheral_address_ = is_peripheral_address;
+		}
 
 		/// Sets the bus error line — @c true for active, @c false for inactive.
-		void set_bus_error(bool);
+		void set_bus_error(bool bus_error) {
+			bus_error_ = bus_error;
+		}
 
 		/// Sets the interrupt lines, IPL0, IPL1 and IPL2.
-		void set_interrupt_level(int);
+		void set_interrupt_level(int interrupt_level) {
+			bus_interrupt_level_ = interrupt_level;
+		}
 
 		/// Sets the bus request line.
-		void set_bus_request(bool);
+		void set_bus_request(bool bus_request) {
+			bus_request_ = bus_request;
+		}
 
 		/// Sets the bus acknowledge line.
-		void set_bus_acknowledge(bool);
+		void set_bus_acknowledge(bool bus_acknowledge) {
+			bus_acknowledge_ = bus_acknowledge;
+		}
 
 	private:
 		T &bus_handler_;
diff --git a/Processors/68000/Implementation/68000Storage.hpp b/Processors/68000/Implementation/68000Storage.hpp
index 5e5db13d7..4965a9ae7 100644
--- a/Processors/68000/Implementation/68000Storage.hpp
+++ b/Processors/68000/Implementation/68000Storage.hpp
@@ -22,7 +22,6 @@ class ProcessorStorage {
 											// are copied into/out of address_[7] upon mode switches.
 
 		RegisterPair32 prefetch_queue_;		// Each word will go into the low part of the word, then proceed upward.
-		bool dtack_ = true;
 
 		// Various status bits.
 		int is_supervisor_;
@@ -34,6 +33,14 @@ class ProcessorStorage {
 		uint_fast32_t negative_flag_;	// The negative flag is set if this value is non-zero.
 		uint_fast32_t trace_flag_;		// The trace flag is set if this value is non-zero.
 
+		// Bus inputs.
+		int bus_interrupt_level_ = 0;
+		bool dtack_ = false;
+		bool is_peripheral_address_ = false;
+		bool bus_error_ = false;
+		bool bus_request_ = false;
+		bool bus_acknowledge_ = false;
+
 		// Generic sources and targets for memory operations;
 		// by convention: [0] = source, [1] = destination.
 		RegisterPair32 effective_address_[2];