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Attempts to make some further semantic sense of the various IWM controls.
This commit is contained in:
Thomas Harte
parent
035f07877c
commit
4197c6f149
@ -12,64 +12,191 @@
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using namespace Apple;
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IWM::IWM(int clock_rate) {
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namespace {
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const int CA0 = 1 << 0;
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const int CA1 = 1 << 1;
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const int CA2 = 1 << 2;
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const int LSTRB = 1 << 3;
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const int ENABLE = 1 << 4;
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const int DRIVESEL = 1 << 5; /* This means drive select, like on the original Disk II. */
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const int Q6 = 1 << 6;
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const int Q7 = 1 << 7;
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const int SEL = 1 << 8; /* This is an additional input, not available on a Disk II, with a confusingly-similar name to SELECT but a distinct purpose. */
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}
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IWM::IWM(int clock_rate) {}
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// MARK: - Bus accessors
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uint8_t IWM::read(int address) {
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access(address);
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printf("IWM r %d (%02x)\n", address&0xf, q_switches_);
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switch(q_switches_) {
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default: return 0x00; // Undefined.
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// Per Inside Macintosh:
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//
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// "Before you can read from any of the disk registers you must set up the state of the IWM so that it
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// can pass the data through to the MC68000's address space where you'll be able to read it. To do that,
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// you must first turn off Q7 by reading or writing dBase+q7L. Then turn on Q6 by accessing dBase+q6H.
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// After that, the IWM will be able to pass data from the disk's RD/SENSE line through to you."
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//
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// My thoughts: I'm unclear on how passing data from RD/SENSE is conflated with reading "any of the disk
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// registers", but the text reads as though the access happens internally but isn't passed on in the case
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// of Q6 and Q7 being in the incorrect state.
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case 0x20: return 0x00; // Data register.
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printf("Read %d: ", address&1);
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case 0x40:
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case 0x60:
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return (mode_&0x1f); // Status register.
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switch(state_ & (Q6 | Q7 | ENABLE)) {
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default:
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printf("Invalid read\n");
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return 0xff;
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case 0x80:
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case 0xa0:
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return 0x80; // Handshake register.
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// "Read all 1s".
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case 0:
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printf("Reading all 1s\n");
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return 0xff;
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case ENABLE: /* Read data register. */
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printf("Reading data register\n");
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return 0x00;
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case Q6: case Q6|ENABLE: {
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/*
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[If A = 0], Read status register:
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bits 0-3: same as mode register.
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bit 5: 1 = either /ENBL1 or /ENBL2 is currently low.
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bit 6: 1 = MZ (reserved for future compatibility; should always be read as 0).
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bit 7: 1 = SENSE input high; 0 = SENSE input low.
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(/ENBL1 is low when the first drive's motor is on; /ENBL2 is low when the second drive's motor is on.
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If the 1-second timer is enabled, motors remain on for one second after being programmatically disabled.)
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*/
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printf("Reading status ([%d] including ", (state_&DRIVESEL) ? 2 : 1);
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// Determine the SENSE input.
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uint8_t sense = 0;
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switch(state_ & (CA2 | CA1 | CA0 | SEL)) {
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default:
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printf("unknown)\n");
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break;
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case 0: // Head step direction.
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printf("head step direction)\n");
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break;
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case SEL: // Disk in place.
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printf("disk in place)\n");
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sense = 0x80;
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break;
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case CA0: // Disk head stepping.
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printf("head stepping)\n");
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break;
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case CA0|SEL: // Disk locked (i.e. write-protect tab).
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printf("disk locked)\n");
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break;
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case CA1: // Disk motor running.
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printf("disk motor running)\n");
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break;
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case CA1|SEL: // Head at track 0.
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printf("head at track 0)\n");
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break;
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case CA1|CA0|SEL: // Tachometer (?)
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printf("tachometer)\n");
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break;
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case CA2: // Read data, lower head.
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printf("data, lower head)\n");
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break;
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case CA2|SEL: // Read data, upper head.
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printf("data, upper head)\n");
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break;
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case CA2|CA1: // Single- or double-sided drive.
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printf("single- or double-sided drive)\n");
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break;
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case CA2|CA1|CA0|SEL: // Drive installed.
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printf("drive installed)\n");
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break;
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}
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return (mode_&0x1f) | sense;
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} break;
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case Q7: case Q7|ENABLE:
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/*
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Read write-handshake register:
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bits 0-5: reserved for future use (currently read as 1).
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bit 6: 1 = write state (cleared to 0 if a write underrun occurs).
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bit 7: 1 = write data buffer ready for data.
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*/
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printf("Reading write handshake\n");
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return 0x1f;
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}
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return 0xff;
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}
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void IWM::write(int address, uint8_t input) {
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access(address);
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printf("IWM w %d (%02x)\n", address&0xf);
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switch(q_switches_) {
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default:
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break;
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switch(state_ & (Q6 | Q7 | ENABLE)) {
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default: break;
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case 0xc0: // Write mode register.
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case Q7|Q6:
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/*
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Write mode register:
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bit 0: 1 = latch mode (should be set in asynchronous mode).
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bit 1: 0 = synchronous handshake protocol; 1 = asynchronous.
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bit 2: 0 = 1-second on-board timer enable; 1 = timer disable.
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bit 3: 0 = slow mode; 1 = fast mode.
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bit 4: 0 = 7Mhz; 1 = 8Mhz (7 or 8 mHz clock descriptor).
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bit 5: 1 = test mode; 0 = normal operation.
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bit 6: 1 = MZ-reset.
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bit 7: reserved for future expansion.
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*/
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mode_ = input;
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printf("IWM mode is now %02x\n", mode_);
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break;
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case 0xd0: // Write data register.
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case Q7|Q6|ENABLE: // Write data register.
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printf("Data register write\n");
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break;
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}
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}
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// MARK: - Switch access
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void IWM::access(int address) {
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switch(address & 0xf) {
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default:
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break;
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// Keep a record of switch state; bits in state_
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// should correlate with the anonymous namespace constants
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// defined at the top of this file — CA0, CA1, etc.
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address &= 0xf;
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const auto mask = 1 << (address >> 1);
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case 0x8: q_switches_ &= ~0x20; break;
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case 0x9: q_switches_ |= 0x20; break;
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case 0xc: q_switches_ &= ~0x40; break;
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case 0xd: q_switches_ |= 0x40; break;
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case 0xe: q_switches_ &= ~0x80; break;
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case 0xf: q_switches_ |= 0x80; break;
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if(address & 1) {
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state_ |= mask;
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} else {
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state_ &= ~mask;
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}
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}
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void IWM::run_for(const Cycles cycles) {
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}
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void IWM::set_select(bool enabled) {
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printf("IWM s %d\n", int(enabled));
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// Augment switch state with the value of the SEL line;
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// it's active low, which is implicitly inverted here for
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// consistency in the meaning of state_ bits.
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if(!enabled) state_ |= 0x100;
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else state_ &= ~0x100;
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}
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// MARK: - Active logic
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void IWM::run_for(const Cycles cycles) {
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}
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@ -42,7 +42,7 @@ class IWM {
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bool read_write_ready_ = true;
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bool write_overran_ = false;
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int q_switches_ = 0;
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int state_ = 0;
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void access(int address);
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};
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