mirror of
https://github.com/TomHarte/CLK.git
synced 2024-12-27 01:31:42 +00:00
Shunted method bodies inline, given that there's no need for a declaration/definition distinction.
This commit is contained in:
Thomas Harte
parent
2b168f7383
commit
42dd27c9b1
@ -36,33 +36,177 @@ struct CRTCBusHandler {
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}
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}
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std::shared_ptr<Outputs::CRT::CRT> crt_;
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void setup_output(float aspect_ratio) {
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crt_.reset(new Outputs::CRT::CRT(1024, 8, Outputs::CRT::DisplayType::PAL50, 1));
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crt_->set_rgb_sampling_function(
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"vec3 rgb_sample(usampler2D sampler, vec2 coordinate, vec2 icoordinate)"
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"{"
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"return vec3(float(texture(texID, coordinate).r) / 255.0);"
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"}");
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}
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void close_output() {
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crt_.reset();
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}
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std::shared_ptr<Outputs::CRT::CRT> get_crt() {
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return crt_;
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}
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private:
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int cycles_;
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bool was_enabled_, was_sync_;
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std::shared_ptr<Outputs::CRT::CRT> crt_;
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};
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class ConcreteMachine:
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public CPU::Z80::Processor<ConcreteMachine>,
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public Machine {
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public:
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ConcreteMachine();
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ConcreteMachine() :
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crtc_counter_(HalfCycles(4)), // This starts the CRTC exactly out of phase with the memory accesses
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crtc_(crtc_bus_handler_) {
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// primary clock is 4Mhz
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set_clock_rate(4000000);
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}
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HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle);
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void flush();
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inline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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// Amstrad CPC timing scheme: assert WAIT for three out of four cycles
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clock_offset_ = (clock_offset_ + cycle.length) & HalfCycles(7);
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set_wait_line(clock_offset_ >= HalfCycles(2));
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void setup_output(float aspect_ratio);
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void close_output();
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// Update the CRTC once every eight half cycles; aiming for half-cycle 4 as
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// per the initial seed to the crtc_counter_, but any time in the final four
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// will do as it's safe to conclude that nobody else has touched video RAM
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// during that whole window
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crtc_counter_ += cycle.length;
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int crtc_cycles = crtc_counter_.divide(HalfCycles(8)).as_int();
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if(crtc_cycles) crtc_.run_for(Cycles(1));
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std::shared_ptr<Outputs::CRT::CRT> get_crt();
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std::shared_ptr<Outputs::Speaker> get_speaker();
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// Stop now if no action is strictly required.
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if(!cycle.is_terminal()) return HalfCycles(0);
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void run_for(const Cycles cycles);
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uint16_t address = cycle.address ? *cycle.address : 0x0000;
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switch(cycle.operation) {
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case CPU::Z80::PartialMachineCycle::ReadOpcode:
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case CPU::Z80::PartialMachineCycle::Read:
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*cycle.value = read_pointers_[address >> 14][address & 16383];
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break;
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void configure_as_target(const StaticAnalyser::Target &target);
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case CPU::Z80::PartialMachineCycle::Write:
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write_pointers_[address >> 14][address & 16383] = *cycle.value;
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break;
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void set_rom(ROMType type, std::vector<uint8_t> data);
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case CPU::Z80::PartialMachineCycle::Output:
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// Check for a gate array access.
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if((address & 0xc000) == 0x4000) {
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switch(*cycle.value >> 6) {
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case 0: printf("Select pen %02x\n", *cycle.value & 0x1f); break;
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case 1: printf("Select colour %02x\n", *cycle.value & 0x1f); break;
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case 2:
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printf("Set mode %d, other flags %02x\n", *cycle.value & 3, (*cycle.value >> 2)&7);
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read_pointers_[0] = (*cycle.value & 4) ? &ram_[0] : os_.data();
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read_pointers_[3] = (*cycle.value & 8) ? &ram_[49152] : basic_.data();
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break;
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case 3: printf("RAM paging?\n"); break;
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}
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}
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// Check for a CRTC access
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if(!(address & 0x4000)) {
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switch((address >> 8) & 3) {
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case 0: crtc_.select_register(*cycle.value); break;
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case 1: crtc_.set_register(*cycle.value); break;
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case 2: case 3: printf("Illegal CRTC write?\n"); break;
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}
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}
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// Check for a PIO access
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if(!(address & 0x800)) {
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switch((address >> 8) & 3) {
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case 0: printf("PSG data: %d\n", *cycle.value); break;
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case 1: printf("Vsync, etc: %02x\n", *cycle.value); break;
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case 2: printf("Key row, etc: %02x\n", *cycle.value); break;
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case 3: printf("PIO control: %02x\n", *cycle.value); break;
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}
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}
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break;
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case CPU::Z80::PartialMachineCycle::Input:
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// Check for a CRTC access
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if(!(address & 0x4000)) {
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switch((address >> 8) & 3) {
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case 0: case 1: printf("Illegal CRTC read?\n"); break;
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case 2: *cycle.value = crtc_.get_status(); break;
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case 3: *cycle.value = crtc_.get_register(); break;
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}
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}
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// Check for a PIO access
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if(!(address & 0x800)) {
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switch((address >> 8) & 3) {
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case 0: printf("[In] PSG data\n"); break;
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case 1: printf("[In] Vsync, etc\n"); break;
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case 2: printf("[In] Key row, etc\n"); break;
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case 3: printf("[In] PIO control\n"); break;
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}
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}
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*cycle.value = 0xff;
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break;
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case CPU::Z80::PartialMachineCycle::Interrupt:
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*cycle.value = 0xff;
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break;
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default: break;
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}
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return HalfCycles(0);
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}
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void flush() {}
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void setup_output(float aspect_ratio) {
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crtc_bus_handler_.setup_output(aspect_ratio);
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}
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void close_output() {
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crtc_bus_handler_.close_output();
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}
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std::shared_ptr<Outputs::CRT::CRT> get_crt() {
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return crtc_bus_handler_.get_crt();
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}
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std::shared_ptr<Outputs::Speaker> get_speaker() {
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return nullptr;
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}
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void run_for(const Cycles cycles) {
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CPU::Z80::Processor<ConcreteMachine>::run_for(cycles);
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}
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void configure_as_target(const StaticAnalyser::Target &target) {
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// Establish reset memory map as per machine model (or, for now, as a hard-wired 464)
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read_pointers_[0] = os_.data();
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read_pointers_[1] = &ram_[16384];
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read_pointers_[2] = &ram_[32768];
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read_pointers_[3] = basic_.data();
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write_pointers_[0] = &ram_[0];
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write_pointers_[1] = &ram_[16384];
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write_pointers_[2] = &ram_[32768];
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write_pointers_[3] = &ram_[49152];
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}
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void set_rom(ROMType type, std::vector<uint8_t> data) {
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// Keep only the two ROMs that are currently of interest.
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switch(type) {
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case ROMType::OS464: os_ = data; break;
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case ROMType::BASIC464: basic_ = data; break;
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default: break;
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}
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}
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private:
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CRTCBusHandler crtc_bus_handler_;
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@ -81,153 +225,3 @@ class ConcreteMachine:
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Machine *Machine::AmstradCPC() {
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return new ConcreteMachine;
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}
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ConcreteMachine::ConcreteMachine() :
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crtc_counter_(HalfCycles(4)), // This starts the CRTC exactly out of phase with the memory accesses
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crtc_(crtc_bus_handler_) {
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// primary clock is 4Mhz
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set_clock_rate(4000000);
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}
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HalfCycles ConcreteMachine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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// Amstrad CPC timing scheme: assert WAIT for three out of four cycles
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clock_offset_ = (clock_offset_ + cycle.length) & HalfCycles(7);
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set_wait_line(clock_offset_ >= HalfCycles(2));
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// Update the CRTC once every eight half cycles; aiming for half-cycle 4 as
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// per the initial seed to the crtc_counter_, but any time in the final four
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// will do as it's safe to conclude that nobody else has touched video RAM
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// during that whole window
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crtc_counter_ += cycle.length;
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int crtc_cycles = crtc_counter_.divide(HalfCycles(8)).as_int();
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if(crtc_cycles) crtc_.run_for(Cycles(1));
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// Stop now if no action is strictly required.
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if(!cycle.is_terminal()) return HalfCycles(0);
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uint16_t address = cycle.address ? *cycle.address : 0x0000;
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switch(cycle.operation) {
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case CPU::Z80::PartialMachineCycle::ReadOpcode:
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case CPU::Z80::PartialMachineCycle::Read:
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*cycle.value = read_pointers_[address >> 14][address & 16383];
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break;
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case CPU::Z80::PartialMachineCycle::Write:
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write_pointers_[address >> 14][address & 16383] = *cycle.value;
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break;
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case CPU::Z80::PartialMachineCycle::Output:
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// Check for a gate array access.
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if((address & 0xc000) == 0x4000) {
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switch(*cycle.value >> 6) {
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case 0: printf("Select pen %02x\n", *cycle.value & 0x1f); break;
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case 1: printf("Select colour %02x\n", *cycle.value & 0x1f); break;
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case 2:
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printf("Set mode %d, other flags %02x\n", *cycle.value & 3, (*cycle.value >> 2)&7);
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read_pointers_[0] = (*cycle.value & 4) ? &ram_[0] : os_.data();
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read_pointers_[3] = (*cycle.value & 8) ? &ram_[49152] : basic_.data();
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break;
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case 3: printf("RAM paging?\n"); break;
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}
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}
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// Check for a CRTC access
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if(!(address & 0x4000)) {
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switch((address >> 8) & 3) {
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case 0: crtc_.select_register(*cycle.value); break;
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case 1: crtc_.set_register(*cycle.value); break;
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case 2: case 3: printf("Illegal CRTC write?\n"); break;
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}
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}
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// Check for a PIO access
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if(!(address & 0x800)) {
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switch((address >> 8) & 3) {
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case 0: printf("PSG data: %d\n", *cycle.value); break;
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case 1: printf("Vsync, etc: %02x\n", *cycle.value); break;
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case 2: printf("Key row, etc: %02x\n", *cycle.value); break;
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case 3: printf("PIO control: %02x\n", *cycle.value); break;
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}
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}
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break;
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case CPU::Z80::PartialMachineCycle::Input:
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// Check for a CRTC access
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if(!(address & 0x4000)) {
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switch((address >> 8) & 3) {
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case 0: case 1: printf("Illegal CRTC read?\n"); break;
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case 2: *cycle.value = crtc_.get_status(); break;
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case 3: *cycle.value = crtc_.get_register(); break;
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}
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}
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// Check for a PIO access
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if(!(address & 0x800)) {
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switch((address >> 8) & 3) {
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case 0: printf("[In] PSG data\n"); break;
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case 1: printf("[In] Vsync, etc\n"); break;
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case 2: printf("[In] Key row, etc\n"); break;
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case 3: printf("[In] PIO control\n"); break;
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}
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}
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*cycle.value = 0xff;
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break;
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case CPU::Z80::PartialMachineCycle::Interrupt:
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*cycle.value = 0xff;
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break;
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default: break;
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}
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return HalfCycles(0);
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}
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void ConcreteMachine::flush() {
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}
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void ConcreteMachine::set_rom(ROMType type, std::vector<uint8_t> data) {
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// Keep only the two ROMs that are currently of interest.
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switch(type) {
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case ROMType::OS464: os_ = data; break;
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case ROMType::BASIC464: basic_ = data; break;
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default: break;
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}
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}
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void ConcreteMachine::setup_output(float aspect_ratio) {
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crtc_bus_handler_.crt_.reset(new Outputs::CRT::CRT(1024, 8, Outputs::CRT::DisplayType::PAL50, 1));
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crtc_bus_handler_.crt_->set_rgb_sampling_function(
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"vec3 rgb_sample(usampler2D sampler, vec2 coordinate, vec2 icoordinate)"
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"{"
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"return vec3(float(texture(texID, coordinate).r) / 255.0);"
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"}");
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}
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void ConcreteMachine::close_output() {
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crtc_bus_handler_.crt_.reset();
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}
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std::shared_ptr<Outputs::CRT::CRT> ConcreteMachine::get_crt() {
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return crtc_bus_handler_.crt_;
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}
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std::shared_ptr<Outputs::Speaker> ConcreteMachine::get_speaker() {
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return nullptr;
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}
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void ConcreteMachine::run_for(const Cycles cycles) {
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CPU::Z80::Processor<ConcreteMachine>::run_for(cycles);
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}
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void ConcreteMachine::configure_as_target(const StaticAnalyser::Target &target) {
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read_pointers_[0] = os_.data();
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read_pointers_[1] = &ram_[16384];
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read_pointers_[2] = &ram_[32768];
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read_pointers_[3] = basic_.data();
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write_pointers_[0] = &ram_[0];
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write_pointers_[1] = &ram_[16384];
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write_pointers_[2] = &ram_[32768];
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write_pointers_[3] = &ram_[49152];
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}
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