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https://github.com/TomHarte/CLK.git
synced 2025-08-08 14:25:05 +00:00
With minor additional logging, it appears the Amiga just keeps resetting itself.
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@@ -68,6 +68,11 @@ class ConcreteMachine:
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cia_a_.run_for(cycle.length);
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cia_a_.run_for(cycle.length);
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cia_b_.run_for(cycle.length);
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cia_b_.run_for(cycle.length);
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// Check for assertion of reset.
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if(cycle.operation & Microcycle::Reset) {
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LOG("Unhandled Reset; PC is around " << PADHEX(8) << mc68000_.get_state().program_counter);
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}
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// Do nothing if no address is exposed.
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// Do nothing if no address is exposed.
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if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return HalfCycles(0);
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if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return HalfCycles(0);
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@@ -139,26 +144,28 @@ class ConcreteMachine:
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// Serial port.
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// Serial port.
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case Write(0x030):
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case Write(0x030):
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LOG("TODO: serial data: " << PADHEX(4) << cycle.value16());
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break;
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case Write(0x032):
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case Write(0x032):
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LOG("TODO: serial; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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LOG("TODO: serial control: " << PADHEX(4) << cycle.value16());
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break;
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break;
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// DMA management.
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// DMA management.
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case Write(0x096):
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case Write(0x096):
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ApplySetClear(dma_control_);
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ApplySetClear(dma_control_);
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LOG("DMA control is now " << std::bitset<16>{interrupt_enable_});
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LOG("DMA control modified by " << PADHEX(4) << cycle.value16() << "; is now " << std::bitset<16>{dma_control_});
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break;
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break;
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// Interrupts.
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// Interrupts.
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case Write(0x09a):
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case Write(0x09a):
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ApplySetClear(interrupt_enable_);
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ApplySetClear(interrupt_enable_);
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update_interrupts();
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update_interrupts();
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LOG("Interrupt enable mask is now " << std::bitset<16>{interrupt_enable_});
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LOG("Interrupt enable mask modified by " << PADHEX(4) << cycle.value16() << "; is now " << std::bitset<16>{interrupt_enable_});
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break;
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break;
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case Write(0x09c):
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case Write(0x09c):
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ApplySetClear(interrupt_requests_);
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ApplySetClear(interrupt_requests_);
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update_interrupts();
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update_interrupts();
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LOG("Interrupt requests are now " << std::bitset<16>{interrupt_enable_});
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LOG("Interrupt request modified by " << PADHEX(4) << cycle.value16() << "; is now " << std::bitset<16>{interrupt_requests_});
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break;
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break;
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// Bitplanes.
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// Bitplanes.
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