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Merge pull request #1335 from TomHarte/ARMDecoding
Add ARM2 operation mapper.
This commit is contained in:
Thomas Harte
GitHub
commit
4c45f4468e
@ -59,7 +59,7 @@ struct YamahaFetcher {
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type(type),
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id(id) {}
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constexpr Event() noexcept {}
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constexpr Event() noexcept = default;
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};
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// State that tracks fetching position within a line.
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469
InstructionSets/ARM/OperationMapper.hpp
Normal file
469
InstructionSets/ARM/OperationMapper.hpp
Normal file
@ -0,0 +1,469 @@
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//
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// OperationMapper.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/02/2024.
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// Copyright © 2024 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "../../Reflection/Dispatcher.hpp"
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namespace InstructionSet::ARM {
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enum class Model {
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ARM2,
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};
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enum class Operation {
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AND, /// Rd = Op1 AND Op2.
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EOR, /// Rd = Op1 EOR Op2.
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SUB, /// Rd = Op1 - Op2.
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RSB, /// Rd = Op2 - Op1.
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ADD, /// Rd = Op1 + Op2.
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ADC, /// Rd = Op1 + Ord2 + C.
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SBC, /// Rd = Op1 - Op2 + C.
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RSC, /// Rd = Op2 - Op1 + C.
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TST, /// Set condition codes on Op1 AND Op2.
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TEQ, /// Set condition codes on Op1 EOR Op2.
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CMP, /// Set condition codes on Op1 - Op2.
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CMN, /// Set condition codes on Op1 + Op2.
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ORR, /// Rd = Op1 OR Op2.
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MOV, /// Rd = Op2
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BIC, /// Rd = Op1 AND NOT Op2.
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MVN, /// Rd = NOT Op2.
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MUL, /// Rd = Rm * Rs
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MLA, /// Rd = Rm * Rs + Rn
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B, /// Add offset to PC; programmer allows for PC being two words ahead.
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BL, /// Copy PC and PSR to R14, then branch. Copied PC points to next instruction.
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LDR, /// Read single byte or word from [base + offset], possibly mutating the base.
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STR, /// Write a single byte or word to [base + offset], possibly mutating the base.
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LDM, /// Read 1–16 words from [base], possibly mutating it.
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STM, /// Write 1-16 words to [base], possibly mutating it.
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SWI, /// Perform a software interrupt.
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CDP, /// Coprocessor data operation.
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MRC, /// Move from coprocessor register to ARM register.
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MCR, /// Move from ARM register to coprocessor register.
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LDC, /// Coprocessor data transfer load.
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STC, /// Coprocessor data transfer store.
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Undefined,
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};
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enum class Condition {
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EQ, NE, CS, CC,
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MI, PL, VS, VC,
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HI, LS, GE, LT,
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GT, LE, AL, NV,
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};
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enum class ShiftType {
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LogicalLeft = 0b00,
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LogicalRight = 0b01,
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ArithmeticRight = 0b10,
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RotateRight = 0b11,
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};
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//
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// Implementation details.
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//
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static constexpr int FlagsStartBit = 20;
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using Flags = uint8_t;
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template <int position>
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constexpr bool flag_bit(uint8_t flags) {
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static_assert(position >= 20 && position < 28);
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return flags & (1 << (position - FlagsStartBit));
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}
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//
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// Methods common to data processing and data transfer.
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//
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struct WithShiftControlBits {
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constexpr WithShiftControlBits(uint32_t opcode) noexcept : opcode_(opcode) {}
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/// The operand 2 register index if @c operand2_is_immediate() is @c false; meaningless otherwise.
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int operand2() const { return opcode_ & 0xf; }
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/// The type of shift to apply to operand 2 if @c operand2_is_immediate() is @c false; meaningless otherwise.
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ShiftType shift_type() const { return ShiftType((opcode_ >> 5) & 3); }
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/// @returns @c true if the amount to shift by should be taken from a register; @c false if it is an immediate value.
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bool shift_count_is_register() const { return opcode_ & (1 << 4); }
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/// The shift amount register index if @c shift_count_is_register() is @c true; meaningless otherwise.
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int shift_register() const { return (opcode_ >> 8) & 0xf; }
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/// The amount to shift by if @c shift_count_is_register() is @c false; meaningless otherwise.
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int shift_amount() const { return (opcode_ >> 7) & 0x1f; }
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protected:
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uint32_t opcode_;
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};
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//
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// Branch (i.e. B and BL).
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//
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struct Branch {
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constexpr Branch(uint32_t opcode) noexcept : opcode_(opcode) {}
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/// The 26-bit offset to add to the PC.
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int offset() const { return (opcode_ & 0xff'ffff) << 2; }
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private:
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uint32_t opcode_;
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};
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//
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// Data processing (i.e. AND to MVN).
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//
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struct DataProcessingFlags {
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constexpr DataProcessingFlags(uint8_t flags) noexcept : flags_(flags) {}
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/// @returns @c true if operand 2 is defined by the @c rotate() and @c immediate() fields;
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/// @c false if it is defined by the @c shift_*() and @c operand2() fields.
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constexpr bool operand2_is_immediate() { return flag_bit<25>(flags_); }
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/// @c true if the status register should be updated; @c false otherwise.
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constexpr bool set_condition_codes() { return flag_bit<20>(flags_); }
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private:
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uint8_t flags_;
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};
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struct DataProcessing: public WithShiftControlBits {
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using WithShiftControlBits::WithShiftControlBits;
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/// The destination register index. i.e. Rd.
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int destination() const { return (opcode_ >> 12) & 0xf; }
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/// The operand 1 register index. i.e. Rn.
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int operand1() const { return (opcode_ >> 16) & 0xf; }
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//
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// Immediate values for operand 2.
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//
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/// An 8-bit value to rotate right @c rotate() places if @c operand2_is_immediate() is @c true; meaningless otherwise.
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int immediate() const { return opcode_ & 0xff; }
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/// The number of bits to rotate @c immediate() by to the right if @c operand2_is_immediate() is @c true; meaningless otherwise.
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int rotate() const { return (opcode_ >> 7) & 0x1e; }
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};
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//
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// MUL and MLA.
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//
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struct MultiplyFlags {
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constexpr MultiplyFlags(uint8_t flags) noexcept : flags_(flags) {}
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/// @c true if the status register should be updated; @c false otherwise.
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constexpr bool set_condition_codes() { return flag_bit<20>(flags_); }
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private:
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uint8_t flags_;
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};
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struct Multiply {
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constexpr Multiply(uint32_t opcode) noexcept : opcode_(opcode) {}
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/// The destination register index. i.e. 'Rd'.
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int destination() const { return (opcode_ >> 16) & 0xf; }
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/// The accumulator register index for multiply-add. i.e. 'Rn'.
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int accumulator() const { return (opcode_ >> 12) & 0xf; }
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/// The multiplicand register index. i.e. 'Rs'.
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int multiplicand() const { return (opcode_ >> 8) & 0xf; }
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/// The multiplier register index. i.e. 'Rm'.
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int multiplier() const { return opcode_ & 0xf; }
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private:
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uint32_t opcode_;
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};
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//
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// Single data transfer (LDR, STR).
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//
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struct SingleDataTransferFlags {
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constexpr SingleDataTransferFlags(uint8_t flags) noexcept : flags_(flags) {}
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constexpr bool offset_is_immediate() { return flag_bit<25>(flags_); }
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constexpr bool pre_index() { return flag_bit<24>(flags_); }
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constexpr bool add_offset() { return flag_bit<23>(flags_); }
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constexpr bool transfer_byte() { return flag_bit<22>(flags_); }
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constexpr bool write_back_address() { return flag_bit<21>(flags_); }
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private:
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uint8_t flags_;
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};
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struct SingleDataTransfer: public WithShiftControlBits {
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using WithShiftControlBits::WithShiftControlBits;
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/// The destination register index. i.e. 'Rd' for LDR.
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int destination() const { return (opcode_ >> 12) & 0xf; }
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/// The destination register index. i.e. 'Rd' for STR.
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int source() const { return (opcode_ >> 12) & 0xf; }
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/// The base register index. i.e. 'Rn'.
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int base() const { return (opcode_ >> 16) & 0xf; }
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/// The immediate offset, if @c offset_is_immediate() was @c true; meaningless otherwise.
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int immediate() const { return opcode_ & 0xfff; }
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};
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//
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// Block data transfer (LDR, STR).
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//
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struct BlockDataTransferFlags {
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constexpr BlockDataTransferFlags(uint8_t flags) noexcept : flags_(flags) {}
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constexpr bool pre_index() { return flag_bit<24>(flags_); }
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constexpr bool add_offset() { return flag_bit<23>(flags_); }
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constexpr bool load_psr() { return flag_bit<22>(flags_); }
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constexpr bool write_back_address() { return flag_bit<21>(flags_); }
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private:
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uint8_t flags_;
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};
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struct BlockDataTransfer: public WithShiftControlBits {
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using WithShiftControlBits::WithShiftControlBits;
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/// The base register index. i.e. 'Rn'.
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int base() const { return (opcode_ >> 16) & 0xf; }
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/// A bitfield indicating which registers to load or store.
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int register_list() const { return opcode_ & 0xffff; }
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};
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//
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// Coprocessor data operation.
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//
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struct CoprocessorDataOperationFlags {
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constexpr CoprocessorDataOperationFlags(uint8_t flags) noexcept : flags_(flags) {}
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constexpr int operation() const { return (flags_ >> (FlagsStartBit - 20)) & 0xf; }
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private:
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uint8_t flags_;
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};
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struct CoprocessorDataOperation {
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constexpr CoprocessorDataOperation(uint32_t opcode) noexcept : opcode_(opcode) {}
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int operand1() { return (opcode_ >> 16) & 0xf; }
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int operand2() { return opcode_ & 0xf; }
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int destination() { return (opcode_ >> 12) & 0xf; }
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int coprocessor() { return (opcode_ >> 8) & 0xf; }
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int information() { return (opcode_ >> 5) & 0x7; }
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private:
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uint32_t opcode_;
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};
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//
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// Coprocessor register transfer.
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//
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struct CoprocessorRegisterTransferFlags {
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constexpr CoprocessorRegisterTransferFlags(uint8_t flags) noexcept : flags_(flags) {}
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constexpr int operation() const { return (flags_ >> (FlagsStartBit - 20)) & 0x7; }
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private:
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uint8_t flags_;
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};
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struct CoprocessorRegisterTransfer {
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constexpr CoprocessorRegisterTransfer(uint32_t opcode) noexcept : opcode_(opcode) {}
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int operand1() { return (opcode_ >> 16) & 0xf; }
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int operand2() { return opcode_ & 0xf; }
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int destination() { return (opcode_ >> 12) & 0xf; }
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int coprocessor() { return (opcode_ >> 8) & 0xf; }
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int information() { return (opcode_ >> 5) & 0x7; }
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private:
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uint32_t opcode_;
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};
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//
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// Coprocessor data transfer.
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//
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struct CoprocessorDataTransferFlags {
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constexpr CoprocessorDataTransferFlags(uint8_t flags) noexcept : flags_(flags) {}
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constexpr bool pre_index() { return flag_bit<24>(flags_); }
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constexpr bool add_offset() { return flag_bit<23>(flags_); }
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constexpr bool transfer_length() { return flag_bit<22>(flags_); }
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constexpr bool write_back_address() { return flag_bit<21>(flags_); }
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private:
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uint8_t flags_;
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};
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struct CoprocessorDataTransfer {
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constexpr CoprocessorDataTransfer(uint32_t opcode) noexcept : opcode_(opcode) {}
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int base() { return (opcode_ >> 16) & 0xf; }
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int source() { return (opcode_ >> 12) & 0xf; }
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int destination() { return (opcode_ >> 12) & 0xf; }
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int coprocessor() { return (opcode_ >> 8) & 0xf; }
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int offset() { return opcode_ & 0xff; }
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private:
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uint32_t opcode_;
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};
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/// Operation mapper; use the free function @c dispatch as defined below.
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struct OperationMapper {
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template <int i, typename SchedulerT> void dispatch(uint32_t instruction, SchedulerT &scheduler) {
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constexpr auto partial = uint32_t(i << 20);
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const auto condition = Condition(instruction >> 28);
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// Cf. the ARM2 datasheet, p.45. Tests below match its ordering
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// other than that 'undefined' is the fallthrough case. More specific
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// page references are provided were more detailed versions of the
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// decoding are depicted.
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// Data processing; cf. p.17.
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if constexpr (((partial >> 26) & 0b11) == 0b00) {
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constexpr auto operation = Operation(int(Operation::AND) + ((partial >> 21) & 0xf));
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scheduler.template perform<operation, i>(
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condition,
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DataProcessing(instruction)
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);
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return;
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}
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// Multiply and multiply-accumulate (MUL, MLA); cf. p.23.
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if constexpr (((partial >> 22) & 0b111'111) == 0b000'000) {
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// This implementation provides only eight bits baked into the template parameters so
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// an additional dynamic test is required to check whether this is really, really MUL or MLA.
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if(((instruction >> 4) & 0b1111) == 0b1001) {
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constexpr bool is_mla = partial & (1 << 21);
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scheduler.template perform<is_mla ? Operation::MLA : Operation::MUL, i>(
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condition,
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Multiply(instruction)
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);
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return;
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}
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}
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// Single data transfer (LDR, STR); cf. p.25.
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if constexpr (((partial >> 26) & 0b11) == 0b01) {
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constexpr bool is_ldr = partial & (1 << 20);
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scheduler.template perform<is_ldr ? Operation::LDR : Operation::STR, i>(
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condition,
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SingleDataTransfer(instruction)
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);
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return;
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}
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// Block data transfer (LDM, STM); cf. p.29.
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if constexpr (((partial >> 25) & 0b111) == 0b100) {
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constexpr bool is_ldm = partial & (1 << 20);
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scheduler.template perform<is_ldm ? Operation::LDM : Operation::STM, i>(
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condition,
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BlockDataTransfer(instruction)
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);
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return;
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}
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// Branch and branch with link (B, BL); cf. p.15.
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if constexpr (((partial >> 25) & 0b111) == 0b101) {
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constexpr bool is_bl = partial & (1 << 24);
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scheduler.template perform<is_bl ? Operation::BL : Operation::B>(
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condition,
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Branch(instruction)
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);
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return;
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}
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// Software interreupt; cf. p.35.
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if constexpr (((partial >> 24) & 0b1111) == 0b1111) {
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scheduler.software_interrupt(condition);
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return;
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}
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// Both:
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// Coprocessor data operation; cf. p. 37; and
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// Coprocessor register transfers; cf. p. 42.
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if constexpr (((partial >> 24) & 0b1111) == 0b1110) {
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if(instruction & (1 << 4)) {
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// Register transfer.
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const auto parameters = CoprocessorRegisterTransfer(instruction);
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constexpr bool is_mrc = partial & (1 << 20);
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scheduler.template perform<is_mrc ? Operation::MRC : Operation::MCR, i>(
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condition,
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parameters
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);
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} else {
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// Data operation.
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const auto parameters = CoprocessorDataOperation(instruction);
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scheduler.template perform<i>(
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condition,
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parameters
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);
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}
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return;
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}
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// Coprocessor data transfers; cf. p.39.
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if constexpr (((partial >> 25) & 0b111) == 0b110) {
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constexpr bool is_ldc = partial & (1 << 20);
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scheduler.template perform<is_ldc ? Operation::LDC : Operation::STC, i>(
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condition,
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CoprocessorDataTransfer(instruction)
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);
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return;
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}
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// Fallback position.
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scheduler.unknown(instruction);
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}
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};
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/// A brief documentation of the interface expected by @c dispatch below; will be a concept if/when this project adopts C++20.
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struct SampleScheduler {
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// General template arguments:
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//
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// (1) Operation, telling the function which operation to perform. Will always be from the subset
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// implied by the operation category; and
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// (2) Flags, an opaque type which can be converted into a DataProcessingFlags, MultiplyFlags, etc,
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// by simply construction, to provide all flags that can be baked into the template parameters.
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//
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// Arguments are ommitted if not relevant.
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//
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// Function arguments:
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//
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// (1) Condition, indicating the condition code associated with this operation; and
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// (2) An operation-specific encapsulation of the operation code for decoding of fields that didn't
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// fit into the template parameters.
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template <Operation, Flags> void perform(Condition, DataProcessing);
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template <Operation, Flags> void perform(Condition, Multiply);
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template <Operation, Flags> void perform(Condition, SingleDataTransfer);
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template <Operation, Flags> void perform(Condition, BlockDataTransfer);
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template <Operation> void perform(Condition, Branch);
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template <Operation, Flags> void perform(Condition, CoprocessorRegisterTransfer);
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template <Flags> void perform(Condition, CoprocessorDataOperation);
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template<Operation, Flags> void perform(Condition, CoprocessorDataTransfer);
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|
||||
// Irregular operations.
|
||||
void software_interrupt(Condition);
|
||||
void unknown(uint32_t opcode);
|
||||
};
|
||||
|
||||
/// Decodes @c instruction, making an appropriate call into @c scheduler.
|
||||
///
|
||||
/// In lieue of C++20, see the sample definition of SampleScheduler above for the expected interface.
|
||||
template <typename SchedulerT> void dispatch(uint32_t instruction, SchedulerT &scheduler) {
|
||||
OperationMapper mapper;
|
||||
Reflection::dispatch(mapper, (instruction >> FlagsStartBit) & 0xff, instruction, scheduler);
|
||||
}
|
||||
|
||||
}
|
||||
@ -1362,9 +1362,9 @@ struct Instruction {
|
||||
bool is_supervisor = false;
|
||||
uint32_t opcode = 0;
|
||||
|
||||
Instruction() noexcept {}
|
||||
Instruction(uint32_t opcode) noexcept : opcode(opcode) {}
|
||||
Instruction(Operation operation, uint32_t opcode, bool is_supervisor = false) noexcept : operation(operation), is_supervisor(is_supervisor), opcode(opcode) {}
|
||||
constexpr Instruction() noexcept = default;
|
||||
constexpr Instruction(uint32_t opcode) noexcept : opcode(opcode) {}
|
||||
constexpr Instruction(Operation operation, uint32_t opcode, bool is_supervisor = false) noexcept : operation(operation), is_supervisor(is_supervisor), opcode(opcode) {}
|
||||
|
||||
// Instruction fields are decoded below; naming is a compromise between
|
||||
// Motorola's documentation and IBM's.
|
||||
|
||||
@ -564,7 +564,7 @@ constexpr Operation rep_operation(Operation operation, Repetition repetition) {
|
||||
/// It cannot natively describe a base of ::None.
|
||||
class ScaleIndexBase {
|
||||
public:
|
||||
constexpr ScaleIndexBase() noexcept {}
|
||||
constexpr ScaleIndexBase() noexcept = default;
|
||||
constexpr ScaleIndexBase(uint8_t sib) noexcept : sib_(sib) {}
|
||||
constexpr ScaleIndexBase(int scale, Source index, Source base) noexcept :
|
||||
sib_(uint8_t(
|
||||
@ -703,7 +703,7 @@ template<bool is_32bit> class Instruction {
|
||||
using ImmediateT = typename std::conditional<is_32bit, uint32_t, uint16_t>::type;
|
||||
using AddressT = ImmediateT;
|
||||
|
||||
constexpr Instruction() noexcept {}
|
||||
constexpr Instruction() noexcept = default;
|
||||
constexpr Instruction(Operation operation) noexcept :
|
||||
Instruction(operation, Source::None, Source::None, ScaleIndexBase(), false, AddressSize::b16, Source::None, DataSize::None, 0, 0) {}
|
||||
constexpr Instruction(
|
||||
|
||||
@ -213,6 +213,7 @@
|
||||
4B1EC716255398B000A1F44B /* Sound.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B1EC714255398B000A1F44B /* Sound.cpp */; };
|
||||
4B1EC717255398B000A1F44B /* Sound.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B1EC714255398B000A1F44B /* Sound.cpp */; };
|
||||
4B1EDB451E39A0AC009D6819 /* chip.png in Resources */ = {isa = PBXBuildFile; fileRef = 4B1EDB431E39A0AC009D6819 /* chip.png */; };
|
||||
4B2005432B804D6400420C5C /* ARMDecoderTests.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4B2005422B804D6400420C5C /* ARMDecoderTests.mm */; };
|
||||
4B2130E2273A7A0A008A77B4 /* Audio.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B2130E0273A7A0A008A77B4 /* Audio.cpp */; };
|
||||
4B2130E3273A7A0A008A77B4 /* Audio.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B2130E0273A7A0A008A77B4 /* Audio.cpp */; };
|
||||
4B228CD524D773B40077EF25 /* CSScanTarget.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4B228CD424D773B30077EF25 /* CSScanTarget.mm */; };
|
||||
@ -1332,6 +1333,8 @@
|
||||
4B1EC714255398B000A1F44B /* Sound.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = Sound.cpp; sourceTree = "<group>"; };
|
||||
4B1EC715255398B000A1F44B /* Sound.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Sound.hpp; sourceTree = "<group>"; };
|
||||
4B1EDB431E39A0AC009D6819 /* chip.png */ = {isa = PBXFileReference; lastKnownFileType = image.png; path = chip.png; sourceTree = "<group>"; };
|
||||
4B2005402B804AA300420C5C /* OperationMapper.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = OperationMapper.hpp; sourceTree = "<group>"; };
|
||||
4B2005422B804D6400420C5C /* ARMDecoderTests.mm */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.objcpp; path = ARMDecoderTests.mm; sourceTree = "<group>"; };
|
||||
4B2130E0273A7A0A008A77B4 /* Audio.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = Audio.cpp; sourceTree = "<group>"; };
|
||||
4B2130E1273A7A0A008A77B4 /* Audio.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Audio.hpp; sourceTree = "<group>"; };
|
||||
4B228CD424D773B30077EF25 /* CSScanTarget.mm */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.objcpp; path = CSScanTarget.mm; sourceTree = "<group>"; };
|
||||
@ -2752,6 +2755,14 @@
|
||||
path = Icons;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B20053D2B804A4F00420C5C /* ARM */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B2005402B804AA300420C5C /* OperationMapper.hpp */,
|
||||
);
|
||||
path = ARM;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B228CD324D773B30077EF25 /* ScanTarget */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
@ -4471,6 +4482,7 @@
|
||||
4B9D0C4E22C7E0CF00DE1AD3 /* 68000RollShiftTests.mm */,
|
||||
4BD388872239E198002D14B5 /* 68000Tests.mm */,
|
||||
4BF7019F26FFD32300996424 /* AmigaBlitterTests.mm */,
|
||||
4B2005422B804D6400420C5C /* ARMDecoderTests.mm */,
|
||||
4B924E981E74D22700B76AF1 /* AtariStaticAnalyserTests.mm */,
|
||||
4BE34437238389E10058E78F /* AtariSTVideoTests.mm */,
|
||||
4BB2A9AE1E13367E001A5C23 /* CRCTests.mm */,
|
||||
@ -5082,6 +5094,7 @@
|
||||
4BE8EB5425C0E9D40040BC40 /* Disassembler.hpp */,
|
||||
4BEDA3B625B25563000C2DBD /* README.md */,
|
||||
4BDA7F7F29C4C179007A10A5 /* 6809 */,
|
||||
4B20053D2B804A4F00420C5C /* ARM */,
|
||||
4B79629B2819681F008130F9 /* M68k */,
|
||||
4BEDA40925B2844B000C2DBD /* M50740 */,
|
||||
4BEDA3B325B25563000C2DBD /* PowerPC */,
|
||||
@ -6334,6 +6347,7 @@
|
||||
4B778F2823A5EEF80000D260 /* Cartridge.cpp in Sources */,
|
||||
4B7752B528217ED30073E2C5 /* SNA.cpp in Sources */,
|
||||
4BEDA3C025B25563000C2DBD /* Decoder.cpp in Sources */,
|
||||
4B2005432B804D6400420C5C /* ARMDecoderTests.mm in Sources */,
|
||||
4B778F4C23A5F2090000D260 /* StaticAnalyser.cpp in Sources */,
|
||||
4B778F2623A5EE350000D260 /* Acorn.cpp in Sources */,
|
||||
4B7752C128217F490073E2C5 /* FAT.cpp in Sources */,
|
||||
|
||||
49
OSBindings/Mac/Clock SignalTests/ARMDecoderTests.mm
Normal file
49
OSBindings/Mac/Clock SignalTests/ARMDecoderTests.mm
Normal file
@ -0,0 +1,49 @@
|
||||
//
|
||||
// ARMDecoderTests.m
|
||||
// Clock Signal
|
||||
//
|
||||
// Created by Thomas Harte on 16/02/2024.
|
||||
// Copyright 2024 Thomas Harte. All rights reserved.
|
||||
//
|
||||
|
||||
#import <XCTest/XCTest.h>
|
||||
|
||||
#include "../../../InstructionSets/ARM/OperationMapper.hpp"
|
||||
|
||||
using namespace InstructionSet::ARM;
|
||||
|
||||
namespace {
|
||||
|
||||
struct Scheduler {
|
||||
template <Operation, Flags> void perform(Condition, DataProcessing) {}
|
||||
template <Operation, Flags> void perform(Condition, Multiply) {}
|
||||
template <Operation, Flags> void perform(Condition, SingleDataTransfer) {}
|
||||
template <Operation, Flags> void perform(Condition, BlockDataTransfer) {}
|
||||
|
||||
template <Operation op> void perform(Condition condition, Branch branch) {
|
||||
printf("Branch %sif %d; add %08x\n", op == Operation::BL ? "with link " : "", int(condition), branch.offset());
|
||||
}
|
||||
template <Operation, Flags> void perform(Condition, CoprocessorRegisterTransfer) {}
|
||||
template <Flags> void perform(Condition, CoprocessorDataOperation) {}
|
||||
template<Operation, Flags> void perform(Condition, CoprocessorDataTransfer) {}
|
||||
|
||||
void software_interrupt(Condition) {}
|
||||
void unknown(uint32_t) {}
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
@interface ARMDecoderTests : XCTestCase
|
||||
@end
|
||||
|
||||
@implementation ARMDecoderTests
|
||||
|
||||
- (void)testXYX {
|
||||
Scheduler scheduler;
|
||||
|
||||
InstructionSet::ARM::dispatch(0xEAE06900, scheduler);
|
||||
// const auto intr = Instruction<Model::ARM2>(1);
|
||||
// NSLog(@"%d", intr.operation());
|
||||
}
|
||||
|
||||
@end
|
||||
@ -203,7 +203,7 @@ class BufferingScanTarget: public Outputs::Display::ScanTarget {
|
||||
struct PointerSet {
|
||||
// This constructor is here to appease GCC's interpretation of
|
||||
// an ambiguity in the C++ standard; cf. https://stackoverflow.com/questions/17430377
|
||||
PointerSet() noexcept {}
|
||||
PointerSet() noexcept = default;
|
||||
|
||||
// Squeezing this struct into 64 bits makes the std::atomics more likely
|
||||
// to be lock free; they are under LLVM x86-64.
|
||||
|
||||
@ -145,7 +145,7 @@ struct Microcycle: public MicrocycleOperationStorage<op> {
|
||||
*/
|
||||
SlicedInt16 *value = nullptr;
|
||||
|
||||
constexpr Microcycle() noexcept {}
|
||||
constexpr Microcycle() noexcept = default;
|
||||
constexpr Microcycle(OperationT dynamic_operation) noexcept {
|
||||
if constexpr (op == Operation::DecodeDynamically) {
|
||||
MicrocycleOperationStorage<op>::operation = dynamic_operation;
|
||||
|
||||
@ -40,7 +40,7 @@ struct Sector {
|
||||
bool has_header_crc_error = false;
|
||||
bool is_deleted = false;
|
||||
|
||||
Sector() noexcept {}
|
||||
Sector() noexcept = default;
|
||||
|
||||
Sector(const Sector &&rhs) noexcept :
|
||||
address(rhs.address),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user