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Ensured BIT takes bits 5 and 3 from the computed address if used on indexed pages. That seems to cover 97 failures out of 100?
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@ -213,9 +213,10 @@ template <class T> class Processor {
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std::vector<MicroOp> all_operations;
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std::vector<MicroOp> fetch_decode_execute;
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MicroOp *fetch_decode_execute_data;
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uint8_t r_step_;
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uint8_t r_step;
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bool is_indexed;
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InstructionPage() : r_step_(1) {}
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InstructionPage() : r_step(1), is_indexed(false) {}
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};
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std::vector<MicroOp> reset_program_;
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std::vector<MicroOp> irq_program_[3];
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@ -682,8 +683,13 @@ template <class T> class Processor {
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assemble_base_page(fd_page_, iy_, true, fdcb_page_);
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assemble_ed_page(ed_page_);
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fdcb_page_.r_step_ = 0;
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ddcb_page_.r_step_ = 0;
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fdcb_page_.r_step = 0;
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fd_page_.is_indexed = true;
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fdcb_page_.is_indexed = true;
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ddcb_page_.r_step = 0;
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dd_page_.is_indexed = true;
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ddcb_page_.is_indexed = true;
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assemble_fetch_decode_execute(base_page_, 4);
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assemble_fetch_decode_execute(dd_page_, 4);
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@ -793,7 +799,7 @@ template <class T> class Processor {
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advance_operation();
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break;
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case MicroOp::DecodeOperation:
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r_ = (r_ & 0x80) | ((r_ + current_instruction_page_->r_step_) & 0x7f);
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r_ = (r_ & 0x80) | ((r_ + current_instruction_page_->r_step) & 0x7f);
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pc_.full += pc_increment_;
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case MicroOp::DecodeOperationNoRChange:
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scheduled_program_counter_ = current_instruction_page_->instructions[operation_ & halt_mask_];
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@ -1299,8 +1305,13 @@ template <class T> class Processor {
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case MicroOp::BIT: {
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uint8_t result = *(uint8_t *)operation->source & (1 << ((operation_ >> 3)&7));
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if(current_instruction_page_->is_indexed) {
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bit53_result_ = temp16_.bytes.high;
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} else {
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bit53_result_ = *(uint8_t *)operation->source;
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}
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sign_result_ = zero_result_ = result;
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bit53_result_ = *(uint8_t *)operation->source; // This is a divergence between FUSE and The Undocumented Z80 Documented.
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half_carry_result_ = Flag::HalfCarry;
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subtract_flag_ = 0;
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parity_overflow_result_ = result ? 0 : Flag::Parity;
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