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https://github.com/TomHarte/CLK.git
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Merge pull request #1025 from TomHarte/AndValidate
Switch to validation via a simple AND mask.
This commit is contained in:
Thomas Harte
GitHub
commit
4e5a6c89b9
@ -37,6 +37,28 @@ constexpr AddressingMode combined_mode(int mode, int reg) {
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return modes[use_reg];
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}
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template <AddressingMode F> struct Mask {
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static constexpr uint32_t value = uint32_t(1 << int(F));
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};
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static constexpr uint32_t NoOperand = Mask<AddressingMode::None>::value;
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template <uint32_t first, uint32_t second> struct TwoOperandMask {
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static constexpr uint32_t value = ((first << 16) & 0xffff0000) | (second & 0x0000ffff);
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};
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template <uint32_t first> struct OneOperandMask {
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static constexpr uint32_t value = TwoOperandMask<first, NoOperand>::value;
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};
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struct NoOperandMask {
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static constexpr uint32_t value = OneOperandMask<NoOperand>::value;
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};
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uint32_t operand_mask(Preinstruction instr) {
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return uint32_t((0x1'0000 << int(instr.mode<0>())) | (0x0'0001 << int(instr.mode<1>())));
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}
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}
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// MARK: - Instruction decoders.
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@ -109,382 +131,337 @@ constexpr Operation Predecoder<model>::operation(OpT op) {
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case ORtoRw: case ORtoMw: return Operation::ORw;
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case ORtoRl: case ORtoMl: return Operation::ORl;
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case EXGRtoR: case EXGAtoA: case EXGRtoA:
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return Operation::EXG;
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default: break;
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}
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return Operation::Undefined;
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}
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template <Model model>
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template <uint8_t op> uint32_t Predecoder<model>::invalid_operands() {
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constexpr auto Dn = Mask< AddressingMode::DataRegisterDirect >::value;
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constexpr auto An = Mask< AddressingMode::AddressRegisterDirect >::value;
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constexpr auto Ind = Mask< AddressingMode::AddressRegisterIndirect >::value;
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constexpr auto PostInc = Mask< AddressingMode::AddressRegisterIndirectWithPostincrement >::value;
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constexpr auto PreDec = Mask< AddressingMode::AddressRegisterIndirectWithPredecrement >::value;
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constexpr auto d16An = Mask< AddressingMode::AddressRegisterIndirectWithDisplacement >::value;
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constexpr auto d8AnXn = Mask< AddressingMode::AddressRegisterIndirectWithIndex8bitDisplacement >::value;
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constexpr auto XXXw = Mask< AddressingMode::AbsoluteShort >::value;
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constexpr auto XXXl = Mask< AddressingMode::AbsoluteLong >::value;
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constexpr auto d16PC = Mask< AddressingMode::ProgramCounterIndirectWithDisplacement >::value;
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constexpr auto d8PCXn = Mask< AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement >::value;
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constexpr auto Imm = Mask< AddressingMode::ImmediateData >::value;
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constexpr auto Quick = Mask< AddressingMode::Quick >::value;
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// A few recurring combinations; terminology is directly from
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// the Programmers' Reference Manual.
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//
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// All modes: the complete set (other than Quick).
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//
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static constexpr auto AllModes = Dn | An | Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl | d16PC | d8PCXn | Imm;
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static constexpr auto AllModesNoAn = AllModes & ~An;
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//
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// Alterable addressing modes (with and without AddressRegisterDirect).
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//
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static constexpr auto AlterableAddressingModes = Dn | An | Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl;
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static constexpr auto AlterableAddressingModesNoAn = AlterableAddressingModes & ~An;
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//
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// Control [flow] addressing modes.
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//
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static constexpr auto ControlAddressingModes = Ind | d16An | d8AnXn | XXXw | XXXl | d16PC | d8PCXn;
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switch(op) {
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default: return NoOperandMask::value;
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case OpT(Operation::ABCD):
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case OpT(Operation::ADDXb): case OpT(Operation::ADDXw): case OpT(Operation::ADDXl):
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return ~TwoOperandMask<
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Dn | PreDec,
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Dn | PreDec
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>::value;
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case ADDtoRb:
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case ANDtoRb: case ANDtoRw: case ANDtoRl:
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case OpT(Operation::CHK):
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case OpT(Operation::CMPb):
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case OpT(Operation::DIVU): case OpT(Operation::DIVS):
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case ORtoRb: case ORtoRw: case ORtoRl:
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case OpT(Operation::MULU): case OpT(Operation::MULS):
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case SUBtoRb:
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return ~TwoOperandMask<
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AllModesNoAn,
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Dn
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>::value;
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case ADDtoRw: case ADDtoRl:
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case OpT(Operation::CMPw): case OpT(Operation::CMPl):
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case SUBtoRw: case SUBtoRl:
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return ~TwoOperandMask<
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AllModes,
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Dn
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>::value;
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case ADDtoMb: case ADDtoMw: case ADDtoMl:
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case ANDtoMb: case ANDtoMw: case ANDtoMl:
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case ORtoMb: case ORtoMw: case ORtoMl:
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case SUBtoMb: case SUBtoMw: case SUBtoMl:
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return ~TwoOperandMask<
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Dn,
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Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl
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>::value;
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case OpT(Operation::ADDAw): case OpT(Operation::ADDAl):
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case OpT(Operation::CMPAw): case OpT(Operation::CMPAl):
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case OpT(Operation::SUBAw): case OpT(Operation::SUBAl):
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case OpT(Operation::MOVEAw): case OpT(Operation::MOVEAl):
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return ~TwoOperandMask<
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AllModes,
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An
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>::value;
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case ADDIb: case ADDIl: case ADDIw:
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case ANDIb: case ANDIl: case ANDIw:
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case BCHGI: case BCLRI: case BSETI:
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case EORIb: case EORIw: case EORIl:
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case ORIb: case ORIw: case ORIl:
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case SUBIb: case SUBIl: case SUBIw:
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return ~TwoOperandMask<
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Imm,
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AlterableAddressingModesNoAn
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>::value;
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case ADDQb:
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case SUBQb:
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return ~TwoOperandMask<
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Quick,
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AlterableAddressingModesNoAn
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>::value;
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case ADDQw: case ADDQl:
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case SUBQw: case SUBQl:
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return ~TwoOperandMask<
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Quick,
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AlterableAddressingModes
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>::value;
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case OpT(Operation::MOVEb):
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return ~TwoOperandMask<
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AllModesNoAn,
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AlterableAddressingModesNoAn
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>::value;
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case OpT(Operation::MOVEw): case OpT(Operation::MOVEl):
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return ~TwoOperandMask<
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AllModes,
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AlterableAddressingModesNoAn
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>::value;
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case OpT(Operation::ANDItoCCR): case OpT(Operation::ANDItoSR):
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case OpT(Operation::Bccw): case OpT(Operation::Bccl):
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case OpT(Operation::BSRl): case OpT(Operation::BSRw):
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case OpT(Operation::EORItoCCR): case OpT(Operation::EORItoSR):
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case OpT(Operation::ORItoCCR): case OpT(Operation::ORItoSR):
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case OpT(Operation::STOP):
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return ~OneOperandMask<
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Imm
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>::value;
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case OpT(Operation::ASLb): case OpT(Operation::ASLw): case OpT(Operation::ASLl):
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case OpT(Operation::ASRb): case OpT(Operation::ASRw): case OpT(Operation::ASRl):
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case OpT(Operation::LSLb): case OpT(Operation::LSLw): case OpT(Operation::LSLl):
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case OpT(Operation::LSRb): case OpT(Operation::LSRw): case OpT(Operation::LSRl):
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case OpT(Operation::ROLb): case OpT(Operation::ROLw): case OpT(Operation::ROLl):
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case OpT(Operation::RORb): case OpT(Operation::RORw): case OpT(Operation::RORl):
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case OpT(Operation::ROXLb): case OpT(Operation::ROXLw): case OpT(Operation::ROXLl):
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case OpT(Operation::ROXRb): case OpT(Operation::ROXRw): case OpT(Operation::ROXRl):
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return ~TwoOperandMask<
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Quick | Dn,
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Dn
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>::value;
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case OpT(Operation::ASLm):
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case OpT(Operation::ASRm):
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case OpT(Operation::LSLm):
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case OpT(Operation::LSRm):
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case OpT(Operation::ROLm):
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case OpT(Operation::RORm):
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case OpT(Operation::ROXLm):
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case OpT(Operation::ROXRm):
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return ~OneOperandMask<
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Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl
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>::value;
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case OpT(Operation::Bccb):
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case OpT(Operation::BSRb):
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case OpT(Operation::TRAP):
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return ~OneOperandMask<
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Quick
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>::value;
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case OpT(Operation::BCHG):
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case OpT(Operation::BCLR):
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case OpT(Operation::BSET):
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case OpT(Operation::EORb): case OpT(Operation::EORw): case OpT(Operation::EORl):
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return ~TwoOperandMask<
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Dn,
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AlterableAddressingModesNoAn
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>::value;
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case OpT(Operation::BTST):
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return ~TwoOperandMask<
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Dn,
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AllModesNoAn
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>::value;
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case CMPIb: case CMPIl: case CMPIw:
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if constexpr (model == Model::M68000) {
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return ~TwoOperandMask<
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Imm,
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Dn | Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl
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>::value;
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}
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[[fallthrough]];
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case BTSTI:
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return ~TwoOperandMask<
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Imm,
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Dn | Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl | d16PC | d8PCXn
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>::value;
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case OpT(Operation::CLRb): case OpT(Operation::CLRw): case OpT(Operation::CLRl):
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case OpT(Operation::NBCD):
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case OpT(Operation::MOVEfromSR):
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case OpT(Operation::NEGXb): case OpT(Operation::NEGXw): case OpT(Operation::NEGXl):
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case OpT(Operation::NEGb): case OpT(Operation::NEGw): case OpT(Operation::NEGl):
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case OpT(Operation::NOTb): case OpT(Operation::NOTw): case OpT(Operation::NOTl):
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case OpT(Operation::Scc):
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case OpT(Operation::TAS):
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return ~OneOperandMask<
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AlterableAddressingModesNoAn
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>::value;
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case OpT(Operation::TSTb):
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if constexpr (model == Model::M68000) {
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return ~OneOperandMask<
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AlterableAddressingModesNoAn
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>::value;
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}
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[[fallthrough]];
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case OpT(Operation::MOVEtoCCR):
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case OpT(Operation::MOVEtoSR):
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return ~OneOperandMask<
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AllModesNoAn
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>::value;
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case OpT(Operation::TSTw): case OpT(Operation::TSTl):
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if constexpr (model == Model::M68000) {
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return ~OneOperandMask<
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AlterableAddressingModesNoAn
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>::value;
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} else {
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return ~OneOperandMask<
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AllModes
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>::value;
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}
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case CMPMb: case CMPMw: case CMPMl:
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return ~TwoOperandMask<
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PostInc,
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PostInc
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>::value;
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case OpT(Operation::DBcc):
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return ~TwoOperandMask<
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Dn,
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Imm
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>::value;
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case EXGRtoR:
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return ~TwoOperandMask<
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Dn,
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Dn
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>::value;
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case EXGAtoA:
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return ~TwoOperandMask<
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An,
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An
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>::value;
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case EXGRtoA:
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return ~TwoOperandMask<
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Dn,
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An
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>::value;
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case OpT(Operation::EXTbtow): case OpT(Operation::EXTwtol):
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case OpT(Operation::SWAP):
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return ~OneOperandMask<
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Dn
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>::value;
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case OpT(Operation::JMP):
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case OpT(Operation::JSR):
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case OpT(Operation::PEA):
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return ~OneOperandMask<
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ControlAddressingModes
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>::value;
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case OpT(Operation::LEA):
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return ~TwoOperandMask<
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ControlAddressingModes,
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An
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>::value;
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case OpT(Operation::LINKw):
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return ~TwoOperandMask<
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An,
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Imm
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>::value;
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case OpT(Operation::NOP):
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case OpT(Operation::RTE):
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case OpT(Operation::RTS):
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case OpT(Operation::TRAPV):
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case OpT(Operation::RTR):
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return ~NoOperandMask::value;
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case OpT(Operation::UNLINK):
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case OpT(Operation::MOVEtoUSP):
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case OpT(Operation::MOVEfromUSP):
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return ~OneOperandMask<
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An
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>::value;
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case MOVEMtoMw: case MOVEMtoMl:
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return ~TwoOperandMask<
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Imm,
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Ind | PreDec | d16An | d8AnXn | XXXw | XXXl
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>::value;
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case MOVEMtoRw: case MOVEMtoRl:
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return ~TwoOperandMask<
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Ind | PostInc | d16An | d8AnXn | XXXw | XXXl | d16PC | d8PCXn,
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Imm
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>::value;
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}
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}
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/// Provides a post-decoding validation step — primarily ensures that the prima facie addressing modes are supported by the operation.
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// TODO: once complete and working, see how ugly it would be to incorpoate these tests into the main
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// decoding switches.
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template <Model model>
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template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated(Preinstruction original) {
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if constexpr (!validate) {
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return original;
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}
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switch(op) {
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default: return original;
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// NBCD.
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case OpT(Operation::NBCD):
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case OpT(Operation::MOVEfromSR):
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case OpT(Operation::TAS):
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switch(original.mode<0>()) {
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default: return original;
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case AddressingMode::AddressRegisterDirect:
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case AddressingMode::ProgramCounterIndirectWithDisplacement:
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case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
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case AddressingMode::ImmediateData:
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case AddressingMode::None:
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return Preinstruction();
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}
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case OpT(Operation::MOVEtoCCR):
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case OpT(Operation::MOVEtoSR):
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switch(original.mode<0>()) {
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default: return original;
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case AddressingMode::AddressRegisterDirect:
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case AddressingMode::None:
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return Preinstruction();
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}
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// The various immediates.
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case EORIb: case EORIl: case EORIw:
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case ORIb: case ORIl: case ORIw:
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case ANDIb: case ANDIl: case ANDIw:
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case SUBIb: case SUBIl: case SUBIw:
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case ADDIb: case ADDIl: case ADDIw:
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switch(original.mode<1>()) {
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default: return original;
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case AddressingMode::AddressRegisterDirect:
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case AddressingMode::ImmediateData:
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case AddressingMode::ProgramCounterIndirectWithDisplacement:
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case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
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case AddressingMode::None:
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return Preinstruction();
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}
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case CMPIb: case CMPIl: case CMPIw:
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switch(original.mode<1>()) {
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default: return original;
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case AddressingMode::ProgramCounterIndirectWithDisplacement:
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case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
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if constexpr (model >= Model::M68010) {
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return original;
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}
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[[fallthrough]];
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case AddressingMode::AddressRegisterDirect:
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case AddressingMode::ImmediateData:
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case AddressingMode::None:
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return Preinstruction();
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}
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// ADD, SUB, MOVE, MOVEA
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case ADDQb: case ADDQw: case ADDQl:
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case SUBQb: case SUBQw: case SUBQl:
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case OpT(Operation::MOVEb): case OpT(Operation::MOVEw): case OpT(Operation::MOVEl):
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case OpT(Operation::MOVEAw): case OpT(Operation::MOVEAl):
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case OpT(Operation::ANDb): case OpT(Operation::ANDw): case OpT(Operation::ANDl):
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case OpT(Operation::EORb): case OpT(Operation::EORw): case OpT(Operation::EORl):
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case OpT(Operation::ORb): case OpT(Operation::ORw): case OpT(Operation::ORl): {
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// TODO: I'm going to need get-size-by-operation elsewhere; use that here when implemented.
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constexpr bool is_byte =
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op == OpT(Operation::MOVEb) || op == ADDQb || op == SUBQb || op == OpT(Operation::EORb);
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switch(original.mode<0>()) {
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default: break;
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case AddressingMode::AddressRegisterDirect:
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if constexpr (!is_byte) {
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break;
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}
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[[fallthrough]];
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case AddressingMode::None:
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return Preinstruction();
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}
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switch(original.mode<1>()) {
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default: return original;
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case AddressingMode::AddressRegisterDirect:
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if constexpr (!is_byte) {
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return original;
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}
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[[fallthrough]];
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case AddressingMode::ImmediateData:
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case AddressingMode::ProgramCounterIndirectWithDisplacement:
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case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
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case AddressingMode::None:
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return Preinstruction();
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}
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}
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|
||||
case ANDtoRb: case ANDtoRw: case ANDtoRl:
|
||||
case ORtoRb: case ORtoRw: case ORtoRl:
|
||||
case SUBtoRb: case SUBtoRw: case SUBtoRl:
|
||||
case ADDtoRb: case ADDtoRw: case ADDtoRl: {
|
||||
constexpr bool is_byte = op == ADDtoRb || op == SUBtoRb || op == SUBtoRb || op == ADDtoRb;
|
||||
|
||||
switch(original.mode<0>()) {
|
||||
default: return original;
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
if constexpr (!is_byte) {
|
||||
return original;
|
||||
}
|
||||
[[fallthrough]];
|
||||
case AddressingMode::None:
|
||||
return Preinstruction();
|
||||
}
|
||||
}
|
||||
|
||||
case ADDtoMb: case ADDtoMw: case ADDtoMl:
|
||||
case SUBtoMb: case SUBtoMw: case SUBtoMl:
|
||||
case ANDtoMb: case ANDtoMw: case ANDtoMl:
|
||||
case ORtoMb: case ORtoMw: case ORtoMl: {
|
||||
// TODO: I'm going to need get-size-by-operation elsewhere; use that here when implemented.
|
||||
constexpr bool is_byte = op == ADDtoMb || op == SUBtoMb || op == ANDtoMb || op == ORtoMb;
|
||||
|
||||
switch(original.mode<0>()) {
|
||||
default: break;
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
if constexpr (!is_byte) {
|
||||
break;
|
||||
}
|
||||
[[fallthrough]];
|
||||
case AddressingMode::None:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
switch(original.mode<1>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::DataRegisterDirect:
|
||||
// TODO: this is per the documentation, but is it true?
|
||||
if constexpr (op == ANDtoMb || op == ANDtoMw || op == ANDtoMl || op == ORtoMb || op == ORtoMw || op == ORtoMl) {
|
||||
return Preinstruction();
|
||||
}
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
if constexpr (!is_byte) {
|
||||
return original;
|
||||
}
|
||||
[[fallthrough]];
|
||||
case AddressingMode::ImmediateData:
|
||||
case AddressingMode::ProgramCounterIndirectWithDisplacement:
|
||||
case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
|
||||
case AddressingMode::None:
|
||||
return Preinstruction();
|
||||
}
|
||||
}
|
||||
|
||||
case OpT(Operation::NOTb): case OpT(Operation::NOTw): case OpT(Operation::NOTl):
|
||||
switch(original.mode<0>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
case AddressingMode::ImmediateData:
|
||||
case AddressingMode::ProgramCounterIndirectWithDisplacement:
|
||||
case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
|
||||
case AddressingMode::None:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
// ADDA, SUBA.
|
||||
case OpT(Operation::ADDAw): case OpT(Operation::ADDAl):
|
||||
case OpT(Operation::SUBAw): case OpT(Operation::SUBAl):
|
||||
switch(original.mode<0>()) {
|
||||
default: break;
|
||||
case AddressingMode::None:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
switch(original.mode<1>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::ImmediateData:
|
||||
case AddressingMode::ProgramCounterIndirectWithDisplacement:
|
||||
case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
|
||||
case AddressingMode::None:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
// LEA, PEA
|
||||
case OpT(Operation::LEA): case OpT(Operation::PEA):
|
||||
switch(original.mode<0>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::None:
|
||||
case AddressingMode::DataRegisterDirect:
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
case AddressingMode::AddressRegisterIndirectWithPostincrement:
|
||||
case AddressingMode::AddressRegisterIndirectWithPredecrement:
|
||||
case AddressingMode::ImmediateData:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
case OpT(Operation::BTST):
|
||||
switch(original.mode<1>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::None:
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
case OpT(Operation::BCHG):
|
||||
case OpT(Operation::BSET): case OpT(Operation::BCLR):
|
||||
case BCHGI: case BSETI: case BCLRI:
|
||||
switch(original.mode<1>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::None:
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
case AddressingMode::ProgramCounterIndirectWithDisplacement:
|
||||
case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
|
||||
case AddressingMode::ImmediateData:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
case BTSTI:
|
||||
switch(original.mode<1>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::None:
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
case AddressingMode::ImmediateData:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
case OpT(Operation::TSTb): case OpT(Operation::TSTw): case OpT(Operation::TSTl):
|
||||
switch(original.mode<0>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
if constexpr (op == OpT(Operation::TSTb)) {
|
||||
return Preinstruction();
|
||||
}
|
||||
[[fallthrough]];
|
||||
|
||||
case AddressingMode::ImmediateData:
|
||||
if constexpr (model < Model::M68020) {
|
||||
return Preinstruction();
|
||||
}
|
||||
return original;
|
||||
|
||||
case AddressingMode::ProgramCounterIndirectWithDisplacement:
|
||||
case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
|
||||
if constexpr (model >= Model::M68010) {
|
||||
return original;
|
||||
}
|
||||
[[fallthrough]];
|
||||
case AddressingMode::None:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
case OpT(Operation::CMPAw): case OpT(Operation::CMPAl):
|
||||
case OpT(Operation::CMPw): case OpT(Operation::CMPl):
|
||||
switch(original.mode<0>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::None:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
case OpT(Operation::CMPb):
|
||||
switch(original.mode<0>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::None:
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
case OpT(Operation::JSR): case OpT(Operation::JMP):
|
||||
switch(original.mode<0>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::DataRegisterDirect:
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
case AddressingMode::AddressRegisterIndirectWithPostincrement:
|
||||
case AddressingMode::AddressRegisterIndirectWithPredecrement:
|
||||
case AddressingMode::ImmediateData:
|
||||
case AddressingMode::None:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
case OpT(Operation::Scc):
|
||||
case OpT(Operation::NEGXb): case OpT(Operation::NEGXw): case OpT(Operation::NEGXl):
|
||||
case OpT(Operation::CLRb): case OpT(Operation::CLRw): case OpT(Operation::CLRl):
|
||||
case OpT(Operation::NEGb): case OpT(Operation::NEGw): case OpT(Operation::NEGl):
|
||||
switch(original.mode<0>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
case AddressingMode::ImmediateData:
|
||||
case AddressingMode::ProgramCounterIndirectWithDisplacement:
|
||||
case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
|
||||
case AddressingMode::None:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
case OpT(Operation::ASLm): case OpT(Operation::ASRm):
|
||||
case OpT(Operation::LSLm): case OpT(Operation::LSRm):
|
||||
case OpT(Operation::ROLm): case OpT(Operation::RORm):
|
||||
case OpT(Operation::ROXLm): case OpT(Operation::ROXRm):
|
||||
switch(original.mode<0>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::DataRegisterDirect:
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
case AddressingMode::ImmediateData:
|
||||
case AddressingMode::ProgramCounterIndirectWithDisplacement:
|
||||
case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
|
||||
case AddressingMode::None:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
case MOVEMtoMw: case MOVEMtoMl:
|
||||
switch(original.mode<1>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::DataRegisterDirect:
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
case AddressingMode::AddressRegisterIndirectWithPostincrement:
|
||||
case AddressingMode::ImmediateData:
|
||||
case AddressingMode::ProgramCounterIndirectWithDisplacement:
|
||||
case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
|
||||
case AddressingMode::None:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
case MOVEMtoRw: case MOVEMtoRl:
|
||||
switch(original.mode<0>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::DataRegisterDirect:
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
case AddressingMode::AddressRegisterIndirectWithPredecrement:
|
||||
case AddressingMode::ImmediateData:
|
||||
case AddressingMode::None:
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
case OpT(Operation::DIVU): case OpT(Operation::DIVS):
|
||||
case OpT(Operation::MULU): case OpT(Operation::MULS):
|
||||
case OpT(Operation::CHK):
|
||||
switch(original.mode<0>()) {
|
||||
default: return original;
|
||||
|
||||
case AddressingMode::AddressRegisterDirect:
|
||||
case AddressingMode::None:
|
||||
return Preinstruction();
|
||||
}
|
||||
}
|
||||
const auto invalid = invalid_operands<op>();
|
||||
const auto observed = operand_mask(original);
|
||||
return (observed & invalid) ? Preinstruction() : original;
|
||||
}
|
||||
|
||||
/// Decodes the fields within an instruction and constructs a `Preinstruction`, given that the operation has already been
|
||||
@ -530,33 +507,6 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
|
||||
// b0–b2 and b3–b5: an effective address;
|
||||
// b6–b8: an opmode, i.e. source + direction.
|
||||
//
|
||||
case OpT(Operation::SUBb): case OpT(Operation::SUBw): case OpT(Operation::SUBl):
|
||||
case OpT(Operation::ANDb): case OpT(Operation::ANDw): case OpT(Operation::ANDl):
|
||||
case OpT(Operation::ORb): case OpT(Operation::ORw): case OpT(Operation::ORl): {
|
||||
|
||||
const auto ea_combined_mode = combined_mode(ea_mode, ea_register);
|
||||
|
||||
// TODO: make this decision outside of this function.
|
||||
if(opmode & 4) {
|
||||
// Dn, <ea>
|
||||
|
||||
return validated<op, validate>(
|
||||
Preinstruction(operation,
|
||||
AddressingMode::DataRegisterDirect, data_register,
|
||||
ea_combined_mode, ea_register));
|
||||
} else {
|
||||
// <ea>, Dn
|
||||
|
||||
return validated<op, validate>(
|
||||
Preinstruction(operation,
|
||||
ea_combined_mode, ea_register,
|
||||
AddressingMode::DataRegisterDirect, data_register));
|
||||
}
|
||||
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
|
||||
case ADDtoRb: case ADDtoRw: case ADDtoRl:
|
||||
case SUBtoRb: case SUBtoRw: case SUBtoRl:
|
||||
case ANDtoRb: case ANDtoRw: case ANDtoRl:
|
||||
@ -653,26 +603,23 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
|
||||
// b9–b11: register Rx (data or address, data if exchange is address <-> data);
|
||||
// b3–b7: an opmode, indicating address/data registers.
|
||||
//
|
||||
case OpT(Operation::EXG):
|
||||
switch((instruction >> 3)&31) {
|
||||
default: return Preinstruction();
|
||||
case EXGRtoR:
|
||||
return validated<op, validate>(
|
||||
Preinstruction(operation,
|
||||
AddressingMode::DataRegisterDirect, data_register,
|
||||
AddressingMode::DataRegisterDirect, ea_register));
|
||||
|
||||
case 0x08: return validated<op, validate>(
|
||||
Preinstruction(operation,
|
||||
AddressingMode::DataRegisterDirect, data_register,
|
||||
AddressingMode::DataRegisterDirect, ea_register));
|
||||
case EXGAtoA:
|
||||
return validated<op, validate>(
|
||||
Preinstruction(operation,
|
||||
AddressingMode::AddressRegisterDirect, data_register,
|
||||
AddressingMode::AddressRegisterDirect, ea_register));
|
||||
|
||||
case 0x09: return validated<op, validate>(
|
||||
Preinstruction(operation,
|
||||
AddressingMode::AddressRegisterDirect, data_register,
|
||||
AddressingMode::AddressRegisterDirect, ea_register));
|
||||
|
||||
case 0x11: return validated<op, validate>(
|
||||
Preinstruction(operation,
|
||||
AddressingMode::DataRegisterDirect, data_register,
|
||||
AddressingMode::AddressRegisterDirect, ea_register));
|
||||
}
|
||||
// TODO: remove conditional from in here.
|
||||
case EXGRtoA:
|
||||
return validated<op, validate>(
|
||||
Preinstruction(operation,
|
||||
AddressingMode::DataRegisterDirect, data_register,
|
||||
AddressingMode::AddressRegisterDirect, ea_register));
|
||||
|
||||
//
|
||||
// MARK: MULU, MULS, DIVU, DIVS.
|
||||
@ -1308,9 +1255,9 @@ Preinstruction Predecoder<model>::decodeC(uint16_t instruction) {
|
||||
|
||||
// 4-105 (p209)
|
||||
switch(instruction & 0x1f8) {
|
||||
case 0x140:
|
||||
case 0x148:
|
||||
case 0x188: Decode(Op::EXG);
|
||||
case 0x140: Decode(EXGRtoR);
|
||||
case 0x148: Decode(EXGAtoA);
|
||||
case 0x188: Decode(EXGRtoA);
|
||||
default: break;
|
||||
}
|
||||
|
||||
|
||||
@ -49,6 +49,7 @@ template <Model model> class Predecoder {
|
||||
// Specific instruction decoders.
|
||||
template <OpT operation, bool validate = true> Preinstruction decode(uint16_t instruction);
|
||||
template <OpT operation, bool validate> Preinstruction validated(Preinstruction original);
|
||||
template <uint8_t op> uint32_t invalid_operands();
|
||||
|
||||
// Extended operation list; collapses into a single byte enough information to
|
||||
// know both the type of operation and how to decode the operands. Most of the
|
||||
@ -90,6 +91,8 @@ template <Model model> class Predecoder {
|
||||
|
||||
ORtoMb, ORtoMw, ORtoMl,
|
||||
ORtoRb, ORtoRw, ORtoRl,
|
||||
|
||||
EXGRtoR, EXGAtoA, EXGRtoA,
|
||||
};
|
||||
|
||||
static constexpr Operation operation(OpT op);
|
||||
|
||||
@ -187,7 +187,7 @@ constexpr int8_t quick(Operation op, uint16_t instruction) {
|
||||
/// as ProgramCounterIndirectWithIndex8bitDisplacement.
|
||||
enum class AddressingMode: uint8_t {
|
||||
/// No adddressing mode; this operand doesn't exist.
|
||||
None = 0b11'111,
|
||||
None = 0b01'101,
|
||||
|
||||
/// Dn
|
||||
DataRegisterDirect = 0b00'000,
|
||||
@ -232,7 +232,7 @@ enum class AddressingMode: uint8_t {
|
||||
ImmediateData = 0b01'100,
|
||||
|
||||
/// .q; value is embedded in the opcode.
|
||||
Quick = 0b11'110,
|
||||
Quick = 0b01'110,
|
||||
};
|
||||
|
||||
/*!
|
||||
|
||||
@ -74,7 +74,6 @@ template <int index> NSString *operand(Preinstruction instruction, uint16_t opco
|
||||
XCTAssertNotNil(decodings);
|
||||
|
||||
Predecoder<Model::M68000> decoder;
|
||||
int skipped = 0;
|
||||
for(int instr = 0; instr < 65536; instr++) {
|
||||
NSString *const instrName = [NSString stringWithFormat:@"%04x", instr];
|
||||
NSString *const expected = decodings[instrName];
|
||||
@ -269,7 +268,7 @@ template <int index> NSString *operand(Preinstruction instruction, uint16_t opco
|
||||
|
||||
// For now, skip any unmapped operations.
|
||||
default:
|
||||
++skipped;
|
||||
XCTAssert(false, @"Operation %d unhandled by test case", int(found.operation));
|
||||
continue;
|
||||
}
|
||||
|
||||
@ -282,8 +281,6 @@ template <int index> NSString *operand(Preinstruction instruction, uint16_t opco
|
||||
XCTAssertFalse(found.mode<0>() == AddressingMode::None && found.mode<1>() != AddressingMode::None, @"Decoding of %@ provided a second operand but not a first", instrName);
|
||||
XCTAssertEqualObjects(instruction, expected, "%@ should decode as %@; got %@", instrName, expected, instruction);
|
||||
}
|
||||
|
||||
NSLog(@"Skipped %d opcodes", skipped);
|
||||
}
|
||||
|
||||
@end
|
||||
|
||||
Loading…
Reference in New Issue
Block a user